6 Pin Configuration and Functions

Figure 6-1 DGN Package, 8-Pin PDSO (Top View)

Table 6-1 Pin Functions

PIN		TYPE⁽¹⁾	DESCRIPTION
NAME	NO.	TYPE⁽¹⁾	DESCRIPTION
DIS/FLT	2	I/O	UCC25800-Q1 disable pin (active low) and fault code output pin.
GND	6	G	The GND pin is the return for all the control and power signals. The layout should separate the power and control signals.
OC/DT	4	I	Voltage on this pin sets the maximum dead-time between the internal switching power devices. The Thevenin resistance on the pin is measured at start-up to set the OCP level.
RT	5	–	Switching frequency setting pin. Connect a resistor from RT pin to GND to set the converter switching frequency. The RT pin can be left open to operate the converter at the default 1.2-MHz switching frequency.
SW	7	–	The switch node of the integrated half-bridge. Connect this pin directly to the transformer.
SYNC	1	I	External clock input for frequency synchronization. The internal MOSFETs are switched synchronized with the rising edge of the SYNC signal, with half of the SYNC pin signal frequency.
VCC	8	I	The input for power and control of UCC25800-Q1. A good high-frequency by-pass capacitor between VCC and GND is needed to ensure high-efficiency, low-EMI design. Use the bypass capacitor layout to minimize the VCC-GND-bypass capacitor loop to reduce the stresses on internal power devices. Referring to Section 11 for layout guidelines.
VREG	3	O	Internal regulated reference. Put a decoupling capacitor right across VREG pin and GND with shortest distance. The VREG pin can also be used as an external supply.
Thermal Pad		–	Connect this pad to GND pin to provide thermal management for the device. Thermal vias are recommended if the design uses multilayer PCB.

(1) I = input, O = output, I/O = input or output, FB = feedback, G = ground, P = power