The VREG pin is an internal linear regulator output and the bias pin for most of the internal circuits. It is important to ensure a good regulated voltage on VREG pin. A low ESL decoupling capacitor is recommended between VREG to GND. The layout should follow the Layout Guidelines.

VREG pin is equipped with two sets of protection functions to prevent the pin from being left open or over loaded from external circuit.

When VREG pin is left open, since there is no decoupling capacitor, the internal linear regulator becomes unstable. The UCC25800-Q1 transformer driver detects this condition, stops the operation, shuts down the internal linear regulator, and enters the latch-off mode. VCC must be recycled to clear this protection.

To prevent VREG pin from being over-loaded, the VREG pin has its own over-current protection. During start-up, when VREG pin voltage is below 1 V, the VREG pin current is limited to 15-mA, to protect the IC from short or over-load conditions. When the VREG pin voltage rises above 1 V, the VREG pin current limit increases to 40 mA for a fast start-up. When the voltage crosses the VREG_OK value, the VREG pin current limit returns to 15 mA. Because the VREG pin provides current for both internal circuit and external circuit, it is recommended to maintain the VREF pin external load to a value less than 1 mA. When the external VREG-pin current is between 1 mA and 15 mA, excessive VREG pin current can cause the VREG pin voltage to drop. During normal operation, if the VREG pin is over loaded and its voltage drops below the VREG_low threshold, the transformer driver shuts down the linear regulator and enters latch-off mode. VCC must be recycled to clear this protection.