ZHCSVO2D June 2008 – July 2024 UCC27200-Q1
PRODUCTION DATA
The bias supply voltage range for which the device is recommended to operate is from 8V to 17V. The lower end of this range is governed by the internal undervoltage-lockout (UVLO) protection feature on the VDD pin supply circuit blocks. Whenever the driver is in UVLO condition when the VDD pin voltage is below the V(ON) supply start threshold, this feature holds the output low, regardless of the status of the inputs. The upper end of this range is driven by the 20V absolute maximum voltage rating of the VDD pin of the device (which is a stress rating). Keeping a 3V margin to allow for transient voltage spikes, the maximum recommended voltage for the VDD pin is 17V. The UVLO protection feature also involves a hysteresis function, which means that when the VDD pin bias voltage has exceeded the threshold voltage and device begins to operate, and if the voltage drops, then the device continues to deliver normal functionality unless the voltage drop exceeds the hysteresis specification VDD(hys). Therefore, ensuring that, while operating at or near the 8V range, the voltage ripple on the auxiliary power supply output is smaller than the hysteresis specification of the device is important to avoid triggering device shutdown. During system shutdown, the device operation continues until the VDD pin voltage has dropped below the V(OFF) threshold, which must be accounted for while evaluating system shutdown timing design requirements. Likewise, at system start-up the device does not begin operation until the VDD pin voltage has exceeded the V(ON) threshold.
The quiescent current consumed by the internal circuit blocks of the device is supplied through the VDD pin. Although this fact is well known, it is important to recognize that the charge for source current pulses delivered by the LO pin is also supplied through the same VDD pin. As a result, every time a current is sourced out of the LO pin, a corresponding current pulse is delivered into the device through the VDD pin. Thus, ensure that a local bypass capacitor is provided between the VDD and GND pins and located as close to the device as possible for the purpose of decoupling is important. A low ESR, ceramic surface-mount capacitor is required. TI recommends using a capacitor in the range from 0.22μF to 4.7μF between VDD and GND. In a similar manner, the current pulses delivered by the HO pin are sourced from the HB pin. Therefore, TI recommends placing a 0.022μF to 0.1μF local decoupling capacitor between the HB and HS pins.