ZHCSTH3D December   2006  – July 2024 UCC27200 , UCC27201

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Stages
      2. 6.3.2 Undervoltage Lockout (UVLO)
      3. 6.3.3 Level Shift
      4. 6.3.4 Boot Diode
      5. 6.3.5 Output Stages
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input Threshold Type
        2. 7.2.2.2 VDD Bias Supply Voltage
        3. 7.2.2.3 Peak Source and Sink Currents
        4. 7.2.2.4 Propagation Delay
        5. 7.2.2.5 Power Dissipation
      3. 7.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 第三方米6体育平台手机版_好二三四免责声明
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 接收文档更新通知
    4. 10.4 支持资源
    5. 10.5 Trademarks
    6. 10.6 静电放电警告
    7. 10.7 术语表
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5.6 Switching Characteristics

VDD = VHB = 12 V, VHS = VSS = 0 V, No load on LO or HO, TA = TJ = –40°C to +150°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PROPAGATION DELAYS
tDLFF VLI falling to VLO falling CLOAD = 0 pF, from VLIT of LI to 90% of LO falling 22 50 ns
tDHFF VHI falling to VHO falling CLOAD = 0 pF, from VIT of HI to 90% of HO falling 22 50 ns
tDLRR VLI rising to VLO rising CLOAD = 0 pF, from VHIT of LI to 10% of LO rising 22 50 ns
tDHRR VHI rising to VHO rising CLOAD = 0 pF, from VHIT of HI to 10% of HO rising 22 50 ns
DELAY MATCHING
tMON LI ON, HI OFF 1 7 ns
tMOFF LI OFF, HI ON 1 7 ns
OUTPUT RISE AND FALL TIME
tR_LO LO rise time CLOAD = 1000 pF, from 10% to 90% 8 ns
tR_HO HO rise time CLOAD = 1000 pF, from 10% to 90% 8 ns
tF_LO LO fall time CLOAD = 1000 pF, from 10% to 90% 7 ns
tF_HO HO fall time CLOAD = 1000 pF, from 10% to 90% 7 ns
tR_LO_p1 LO rise time (3 V to 9 V) CLOAD = 0.1 μF, (3V to 9V) 0.26 0.6 μs
tR_HO_p1 HO rise time (3 V to 9 V) CLOAD = 0.1 μF, (3V to 9V) 0.26 0.6 μs
tF_LO_p1 LO fall time (9 V to 3 V) CLOAD = 0.1 μF, (9V to 3V) 0.22 0.6 μs
tF_HO_p1 HO fall time (9 V to 3 V) CLOAD = 0.1 μF, (9V to 3V) 0.22 0.6 μs
MISCELLANEOUS
tIN_PW Minimum input pulse width that changes the output  LO 50 ns
tIN_PW Minimum input pulse width that changes the output  HO 50 ns
tOFF_BSD Bootstrap diode turnoff time(1)(2) IF = 20 mA, IREV = 0.5 A(3) 20 ns
(1) Parameter not tested in production.
(2) Typical values for TA = 25°C.
(3) IF: Forward current applied to bootstrap diode, IREV: Reverse current applied to bootstrap diode.
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