The output stages are the interface from level shifter output to the power MOSFETs in the power train. High slew rate, low resistance, and high peak current capability of both outputs allow for efficient switching of the power MOSFETs. The low-side output stage is referenced to VSS and the high-side is referenced to HS. The device output stages are robust to handle harsh environment, such as –2 V transient for 100 ns. The device can also sustain positive transients on the outputs. The device output stages feature a pull-up structure which delivers the highest peak source current when it is most needed, during the Miller plateau region of the power switch turn on transition. The output pull-up and pull-down structure of the device is totem pole NMOS-PMOS structure.