ZHCSJ21B November 2018 – May 2022 UCC27282
PRODUCTION DATA
The recommended bias supply voltage range for UCC27282 is from 5.5 V to 16 V. The lower end of this range is governed by the internal under voltage-lockout (UVLO) protection feature, 5 V typical, of the VDD supply circuit block. The upper end of this range is driven by the 16-V recomended maximum voltage rating of the VDD. It is recommended that voltage on VDD pin should be lower than maximum recommended voltage. In some transient condition it is not possible to keep this voltage below recommended maximum level and therefore absolute maximum voltage rating of the UCC27282 is 20 V.
The UVLO protection feature also involves a hysteresis function. This means that once the device is operating in normal mode, if the VDD voltage drops, the device continues to operate in normal mode as far as the voltage drop do not exceeds the hysteresis specification, VDDHYS. If the voltage drop is more than hysteresis specification, the device shuts down. Therefore, while operating at or near the 5.5-V range, the voltage ripple on the auxiliary power supply output should be smaller than the hysteresis specification of UCC27282 to avoid triggering device shutdown.
A local bypass capacitor should be placed between the VDD and GND pins. This capacitor should be located as close to the device as possible. A low ESR, ceramic surface mount capacitor is recommended. It is recommended to use two capacitors across VDD and GND: a low capacitance ceramic surface-mount capacitor for high frequency filtering placed very close to VDD and GND pin, and another high capacitance value surface-mount capacitor for device bias requirements. In a similar manner, the current pulses delivered by the HO pin are sourced from the HB pin. Therefore, two capacitors across the HB to HS are recommended. One low value small size capacitor for high frequency filtering and another one high capacitance value capacitor to deliver HO pulses.
UCC27282 has enable/disable functionality through EN pin. Therefore, signal at the EN pin should be as clean as possible. If EN pin is not used, then it is recommended to connect the pin to VDD pin. If EN pin is pulled up through a resistor, then the pull-up resistor needs to be strong. In noise prone applications, it is recommended to filter the EN pin with small capacitor, such as X7R 0402 1nF.
In power supplies where noise is very dominant and there is space on the PWB (Printed Wiring Board), it is recommended to place a small RC filter at the inputs. This allows for improving the overall performance of the design. In such applications. it is also recommended to have a place holder for power MOSFET external gate resistor. This resistor allows the control of not only the drive capability but also the slew rate on HS, which impacts the performance of the high-side circuit. If diode is used across the external gate resistor, it is recommended to use a resistor in series with the diode, which provides further control of fall time.
In power supply applications such as motor drives, there exist lot of transients through-out the system. This sometime causes over voltage and under voltage spikes on almost all pins of the gate driver device. To increase the robustness of the design, it is recommended that the clamp diode should be used on HO and LO pins. If user does not wish to use power MOSFET parasitic diode, external clamp diode on HS pin is recommended, which needs to be high voltage high current type (same rating as MOSFET) and very fast acting. The leakage of these diodes across the temperature needs to be minimal.
In power supply applications where it is almost certain that there is excessive negative HS voltage, it is recommended to place a small resistor between the HS pin and the switch node. This resistance helps limit current into the driver device up to some extent. This resistor will impact the high side drive capability and therefore needs to be considered carefully.