The total power loss in gate driver device such as the UCC27284-Q1 is the summation of the power loss in different functional blocks of the gate driver device. These power loss components are explained in this section.

1. Equation 4 describes how quiescent currents (I_DD and I_HB) affect the static power losses, P_QC.
   Equation 4.

   it is not shown here, but for better approximation, add no load operating current, I_DDO and I_HBO in above equation.

2. Equation 5 shows how high-side to low-side leakage current (I_HBS) affects level-shifter losses (P_IHBS).
   Equation 5.

   where

   • D is the high-side MOSFET duty cycle
   • V_HB is the sum of input voltage and voltage across bootstrap capacitor.
3. Equation 6 shows how MOSFETs gate charge (Q_G) affects the dynamic losses, P_QG.
   Equation 6.

   where

   • Q_G is the total MOSFET gate charge
   • f_SW is the switching frequency
   • R_{GD_R} is the average value of pullup and pulldown resistor
   • R_GATE is the external gate drive resistor
   • R_GFET(int) is the power MOSFETs internal gate resistor

   Assume there is no external gate resistor in this example. The average value of maximum pull-up and pull down resistance of the driver output section is approximately 4 Ω. Substitute the application values to calculate the dynamic loss due to gate charge, which is 160 mW here.

4. Equation 7 shows how parasitic level-shifter charge (Q_P) on each switching cycle affects dynamic losses, (P_LS) during high-side switching.
   Equation 7.

   For this example and simplicity, it is assumed that value of parasitic charge Q_P is 1 nC. Substituting values results in 24.6 mW as level shifter dynamic loss. This estimate is very high for level shifter dynamic losses.

The sum of all the losses is 191.85 mW as a total gate driver loss. As shown in this example, in most applications the dynamic loss due to gate charge dominates the total power loss in gate driver device. For gate drivers that include bootstrap diode, one should also estimate losses in bootstrap diode. Diode forward conduction loss is computed as product of average forward voltage drop and average forward current.

Equation 8 estimates the maximum allowable power loss of the device for a given ambient temperature.

Equation 8.

where

• P_MAX is the maximum allowed power dissipation in the gate driver device
• T_J is the recommended maximum operating junction temperature
• T_A is the ambient temperature of the gate driver device
• R_θJA is the junction-to-ambient thermal resistance

To better estimate the junction temperature of the gate driver device in the application, it is recommended to first accurately measure the case temperature and then determine the power dissipation in a given application. Then use ψ_JT to calculate junction temperature. After estimating junction temperature and measuring ambient temperature in the application, calculate θ_{JA(effective)}. Then, if design parameters (such as the value of an external gate resistor or power MOSFET) change during the development of the project, use θ_{JA(effective)} to estimate how these changes affect junction temperature of the gate driver device.

For detailed information regarding the thermal information table, please refer to the Semiconductor and Device Package Thermal Metrics application report.