ZHCSL22B March   2020  – May 2022 UCC27284-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Start-Up and UVLO
      2. 7.3.2 Input Stage
      3. 7.3.3 Level Shifter
      4. 7.3.4 Output Stage
      5. 7.3.5 Negative Voltage Transients
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select Bootstrap and VDD Capacitor
        2. 8.2.2.2 Estimate Driver Power Losses
        3. 8.2.2.3 Selecting External Gate Resistor
        4. 8.2.2.4 Delays and Pulse Width
        5. 8.2.2.5 External Bootstrap Diode
        6. 8.2.2.6 VDD and Input Filter
        7. 8.2.2.7 Transient Protection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 第三方米6体育平台手机版_好二三四免责声明
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

GUID-13BCC348-389A-4AEE-8208-5B60216DAD5D-low.gifFigure 5-1 D Package8-Pin SOICTop View
GUID-9C424A05-372F-4E87-9E97-59D82FFB2357-low.gif Figure 5-2 DDA Package8-Pin SOIC with PowerPADTop View
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
Name DRC DRM DPR
EN 6 — — I Enable input. When this pin is pulled high, it will enable the driver. If left floating or pulled low, it disables the driver. A 1-nF filter capacitor is recommended for high-noise systems.
HB 3 2 2 P High-side bootstrap supply. The bootstrap diode is on-chip but the external bootstrap capacitor is required. Connect positive side of the bootstrap capacitor to this pin. Typical recommended value of HB bypass capacitor is 0.1 μF. This value primarily depends on the gate charge of the high-side MOSFET. When using external boot diode, connect cathode of the diode to this pin.
HI 7 5 7 I High-side input
HO 4 3 3 O High-side output. Connect to the gate of the high-side power MOSFET or one end of external gate resistor, when used.
HS 5 4 4 P High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this pin.
LI 8 6 8 I Low-side input
LO 10 8 10 O Low-side output. Connect to the gate of the low-side power MOSFET or one end of external gate resistor, when used.
NC 2 n/a 5,6 — Not connected internally
VDD 1 1 1 P Positive supply to the low-side gate driver. Decouple this pin to VSS. Typical decoupling capacitor value is 1 μF. When using an external boot diode, connect the anode to this pin.
VSS 9 7 9 G Negative supply terminal for the device which is generally the system ground
Thermal pad — — — — Connect to a large thermal mass trace (generally IC ground plane) to improve thermal performance. This can only be electrically connected to VSS.
(1) P = Power, G = Ground, I = Input, O = Output, I/O = Input/Output
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |