To improve the switching characteristics and efficiency of a design, the following layout rules must be followed.
- Locate the driver as close as possible to the MOSFETs.
- Locate the VDD – VSS and
VHB-VHS (bootstrap) capacitors as close as possible to
the device.
- Pay close attention to the GND trace. Use the thermal pad of the DRM package as GND by connecting it to the VSS pin (GND). The GND trace from the driver goes directly to the source of the MOSFET, but must not be in the high current path of the MOSFET drain or source current.
- Use similar rules for the HS node as for GND for the high-side driver.
- For systems using multiple UCC27311A devices, TI recommends that dedicated
decoupling capacitors be located at VDD-VSS for each
device.
- Care must be taken to avoid placing VDD traces close to LO, HS, and HO signals.
- Use wide traces for LO and HO closely following
the associated GND or HS traces. A width of 60 to 100mils is preferable where
possible.
- Use as least two or more vias if the driver outputs or SW node must be routed from one layer to another. For GND, the number of vias must be a consideration of the thermal pad requirements as well as parasitic inductance.
- Avoid LI and HI (driver input) going close to the HS node or any other high dV/dT traces that can induce significant noise into the relatively high impedance leads.
A poor layout can cause a significant drop in efficiency or system malfunction, and it can even lead to decreased reliability of the whole system.