Power dissipation of the gate driver has two portions as shown in equation below:

Equation 1.

The DC portion of the power dissipation is P_DC = I_Q× VDD where I_Q is the quiescent current for the driver. The quiescent current is the current consumed by the device to bias all internal circuits such as input stage, reference voltage, logic circuits, protections,and so on, and any current associated with switching of internal devices when the driver output changes state (such as charging and discharging of internal parasitic capacitances, parasitic shoot-through). The UCC27332-Q1 features low quiescent currents (less than 1 mA) and contains internal logic to minimize any shoot-through (PMOS to NMOS and vice versa) in the output driver stage. Thus, the effect of the P_DC on the total power dissipation within the gate driver can be assumed to be negligible. In practice this is the power consumed by driver when its output is disconnected from the gate of power switch.

As explained in earlier sections, the output stage of the gate driver is based on PMOS and NMOS. These NMOS and PMOS are designed in such a way that they offer very low resistance during switching. And therefore they have very low drop-out. The power dissipated in the gate driver package during switching (P_SW) depends on the following factors:

• Gate charge required of the power device (usually a function of the drive voltage V_G, which is very close to input bias supply voltage VDD due to low V_OUT drop-out)
• Switching frequency
• Power MOSFET internal and external gate resistor

When a driver device is tested with a discrete, capacitive load it is a fairly simple matter to calculate the power that is required from the bias supply. The energy that must be transferred from the bias supply to charge the capacitor is given by:

Equation 2.

where

• C_LOAD is load capacitor and V_DD is bias voltage feeding the driver.

There is an equal amount of energy dissipated when the capacitor is discharged. During turnoff the energy stored in capacitor is fully dissipated in drive circuit. This leads to a total power loss during switching cycle given by the following:

Equation 3.

where

• ƒ_SW is the switching frequency

The switching load presented by a power FET can be converted to an equivalent capacitance by examining the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the added charge needed to swing the drain voltage of the power device as it switches between the ON and OFF states. Most manufacturers provide specifications of typical and maximum gate charge, in nC, to switch the device under specified conditions. Using the gate charge Q_g, one can determine the power that must be dissipated when charging a capacitor. This is done by using the equivalence, Q_g = C_LOADV_DD, to provide the following equation for power:

Equation 4.

This power P_G is dissipated in the resistive elements of the circuit when the MOSFET and IGBT is being turned on or off. Half of the total power is dissipated when the load capacitor is charged during turnon, and the other half is dissipated when the load capacitor is discharged during turn-off. When no external gate resistor is employed between the driver IC and MOSFET, this power is completely dissipated inside the driver IC. With the use of external gate drive resistors, the power dissipation is shared between the internal resistance of driver and external gate resistor in accordance to the ratio of the resistances (more power dissipated in the higher resistance component). Based on this simplified analysis, the driver power dissipation during switching is calculated as shown in following equation. This primarily applies to those applications where total external gate resistor is significantly large to limit the peak current of the gate driver.

Equation 5.

where

• R_OFF = R_OL and R_ON (effective resistance of pullup structure)