ZHCSHR6A March   2018  – January 2024 UCC27511A

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 VDD and Undervoltage Lockout
      2. 6.3.2 Operating Supply Current
      3. 6.3.3 Input Stage
      4. 6.3.4 Enable Function
      5. 6.3.5 Output Stage
      6. 6.3.6 Low Propagation Delays
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input-to-Output Logic
        2. 7.2.2.2 Input Threshold Type
        3. 7.2.2.3 VDD Bias Supply Voltage
        4. 7.2.2.4 Peak Source and Sink Currents
        5. 7.2.2.5 Enable and Disable Function
        6. 7.2.2.6 Propagation Delay
        7. 7.2.2.7 Thermal Information
        8. 7.2.2.8 Power Dissipation
      3. 7.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 第三方米6体育平台手机版_好二三四免责声明
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
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5.6 Switching Characteristics

VDD = 12 V, TA = TJ = –40°C to 140°C, 1-µF capacitor from VDD to GND. Currents are positive into, negative out of the specified terminal. See Figure 5-1, Figure 5-2, Figure 5-3, and Figure 5-4
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
trRise time(1)VDD = 12 V
C(LOAD) = 1.8 nF, connected to OUTH and OUTL pins tied together		812ns
VDD = 4.5 V
C(LOAD) = 1.8 nF		1622
tfFall time(1)VDD = 12 V
C(LOAD) = 1.8 nF, connected to OUTH and OUTL pins tied together		711ns
VDD = 4.5 V
C(LOAD) = 1.8 nF		711
td(1)IN+ to output propagation delay(1)VDD = 12 V
5-V input pulse C(LOAD) = 1.8 nF, connected to OUTH and OUTL pins tied together		41323ns
VDD = 4.5 V
5-V input pulse C(LOAD) = 1.8 nF, connected to OUTH and OUTL pins tied together		41526
td(2)IN– to output propagation delay(1)VDD = 12 V
C(LOAD) = 1.8 nF, connected to OUTH and OUTL pins tied together		41323ns
VDD = 4.5 V
C(LOAD) = 1.8 nF, connected to OUTH and OUTL pins tied together		41930
(1) See timing diagrams in Figure 5-1, Figure 5-2, Figure 5-3, and Figure 5-4.
GUID-ABB0F1E2-13E4-4861-BE3C-92A2ABEBDB36-low.gifFigure 5-1 Non-Inverting Configuration (PWM Input to IN+ pin (IN– Pin Tied to GND), Output Represents OUTH and OUTL Pins Tied Together in the UCC27511A)
GUID-90DEA36C-C6F6-4D99-8E30-C9E11115B626-low.gifFigure 5-2 Inverting Configuration (PWM Input to IN– Pin (IN+ Pin Tied to VDD), Output Represents OUTH and OUTL Pins Tied Together in the UCC27511A)
GUID-50A209EE-7305-4F97-91C2-D9869DAB5BC9-low.gifFigure 5-3 Enable And Disable Function Using IN+ Pin (Enable and Disable Signal Applied to IN+ Pin, PWM Input to IN– Pin, Output Represents OUTH and OUTL Pins Tied Together in the UCC27511A)
GUID-96BE507D-4A63-4EBF-BDA0-BAD608B2D501-low.gifFigure 5-4 Enable and Disable Function Using IN– Pin (Enable and Disable Signal Applied to IN– Pin, PWM Input to IN+ Pin, Output Represents OUTH and OUTL Pins Tied Together in the UCC27511A)
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