The bias supply voltage range for which the UCC27511 and UCC27512 device is rated to operate is from 4.5 V to 18 V. The lower end of this range is governed by the internal undervoltage-lockout (UVLO) protection feature on the V_DD pin supply circuit blocks. Whenever the driver is in UVLO condition when the V_DD pin voltage is below the V_(ON) supply start threshold, this feature holds the output low, regardless of the status of the inputs. The upper end of this range is driven by the 20-V absolute maximum voltage rating of the V_DD pin of the device (which is a stress rating). Keeping a 2-V margin to allow for transient voltage spikes, the maximum recommended voltage for the V_DD pin is 18 V.

The UVLO protection feature also involves a hysteresis function. This means that when the V_DD pin bias voltage has exceeded the threshold voltage and device begins to operate, and if the voltage drops, then the device continues to deliver normal functionality unless the voltage drop exceeds the hysteresis specification V_DD(hys). Therefore, ensuring that, while operating at or near the 4.5 V range, the voltage ripple on the auxiliary power supply output is smaller than the hysteresis specification of the device is important to avoid triggering device shutdown.

During system shutdown, the device operation continues until the V_DD pin voltage has dropped below the V_(OFF) threshold which must be accounted for while evaluating system shutdown timing design requirements. Likewise, at system startup, the device does not begin operation until the V_DD pin voltage has exceeded above the V_(ON) threshold.

The quiescent current consumed by the internal circuit blocks of the device is supplied through the V_DD pin. Although this fact is well known, recognizing that the charge for source current pulses delivered by the OUTH pin is also supplied through the same V_DD pin is important. As a result, every time a current is sourced out of the output pins (OUTH), a corresponding current pulse is delivered into the device through the V_DD pin. Thus ensuring that local bypass capacitors are provided between the V_DD and GND pins and located as close to the device as possible for the purpose of decoupling is important. A low ESR, ceramic surface mount capacitor is a must. TI recommends to have 2 capacitors; a 100-nF ceramic surface-mount capacitor which can be nudged very close to the pins of the device and another surface-mount capacitor of few microfarads added in parallel.