12.1 Layout Guidelines

Proper PCB layout is extremely important in a high-current fast-switching circuit to provide appropriate device operation and design robustness. The UCC27517A-Q1 gate driver incorporates short-propagation delays and powerful output stages capable of delivering large current peaks with very fast rise and fall times at the gate of the power switch to facilitate voltage transitions very quickly. At higher V_DD voltages, the peak-current capability is even higher (4-A, 4-A peak current is at V_DD = 12 V). Very high di/dt causes unacceptable ringing if the trace lengths and impedances are not well controlled. The following circuit layout guidelines are strongly recommended when designing with these high-speed drivers.

• Locate the driver device as close as possible to the power device in order to minimize the length of high-current traces between the output pins and the gate of the power device.
• Locate the V_DD bypass capacitors between V_DD and GND as close as possible to the driver with minimal trace length to improve the noise filtering. These capacitors support high-peak current being drawn from V_DD during turnon of power MOSFET. The use of low inductance SMD components such as chip resistors and chip capacitors is highly recommended.
• The turnon and turnoff current-loop paths (driver device, power MOSFET and V_DD bypass capacitor) should be minimized as much as possible in order to keep the stray inductance to a minimum. High dI/dt is established in these loops at two instances — during turnon and turnoff transients, which will induce significant voltage transients on the output pin of the driver device and gate of the power switch.
• Wherever possible parallel the source and return traces, taking advantage of flux cancellation.
• Separate power traces and signal traces, such as output and input signals.
• Star-point grounding is a good way to minimize noise coupling from one current loop to another. The GND of the driver should be connected to the other circuit nodes such as source of power switch or the ground of PWM controller at one, single point. The connected paths should be as short as possible to reduce inductance and be as wide as possible to reduce resistance.
• Use a ground plane to provide noise shielding. Fast rise and fall times at OUT may corrupt the input signals during transition. The ground plane must not be a conduction path for any current loop. Instead the ground plane must be connected to the star-point with one single trace to establish the ground potential. In addition to noise shielding, the ground plane can help in power dissipation as well.
• In noisy environments, tying the unused input pin of the UCC27517A-Q1 to V_DD (in case of IN+) or GND (in case of IN–) using short traces in order to ensure that the output is enabled and to prevent noise from causing malfunction in the output is necessary.

12.2 Layout Example

Figure 26. UCC27517ADBVQ1 in Noninverting Configuration

12.3 Thermal Considerations

The useful range of a driver is greatly affected by the drive-power requirements of the load and the thermal characteristics of the package. In order for a gate driver to be useful over a particular temperature range the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. The thermal metrics for the driver package is summarized in the Specifications section of the datasheet. For detailed information regarding the thermal information table, refer to the Application Note from Texas Instruments entitled Semiconductor and IC Package Thermal Metrics (SPRA953).

The UCC27517A-Q1 is offered in SOT-23, 5-pin package (DBV). The Thermal Information table summarizes the thermal performance metrics related to the package. θ_JA metric should be used for comparison of power dissipation between different packages. The ψ_JT and ψ_JB metrics should be used when estimating the die temperature during actual application measurements.

The DBV package heat removal occurs primarily through the leads of the device and the PCB traces connected to the leads.

12.4 Power Dissipation

Power dissipation of the gate driver has two portions as shown in Equation 1.

Equation 1.

The DC portion of the power dissipation is P_DC = I_Q x V_DD where I_Q is the quiescent current for the driver. The quiescent current is the current consumed by the device to bias all internal circuits such as input stage, reference voltage, logic circuits, protections, and also any current associated with switching of internal devices when the driver output changes state (such as charging and discharging of parasitic capacitances, parasitic shoot-through etc). The UCC27517-Q1 device features very-low quiescent currents (less than 1 mA, refer Figure 7) and contains internal logic to eliminate any shoot-through in the output-driver stage. Thus the effect of the P_DC on the total power dissipation within the gate driver can be safely assumed to be negligible.

The power dissipated in the gate-driver package during switching (P_SW) depends on the following factors:

• Gate charge required of the power device (usually a function of the drive voltage V_G, which is very close to input bias supply voltage V_DD due to low V_OH drop-out).
• Switching frequency.
• Use of external-gate resistors.

When a driver device is tested with a discrete, capacitive load calculating the power that is required from the bias supply is fairly easy. The energy that must be transferred from the bias supply to charge the capacitor is given by Equation 2.

Equation 2.

where

• C_LOAD is load capacitor
• V_DD is bias voltage feeding the driver

There is an equal amount of energy dissipated when the capacitor is charged. This leads to a total power loss given by Equation 3.

Equation 3.

where

• ƒ_SW is the switching frequency

The switching load presented by a power MOSFET/IGBT is converted to an equivalent capacitance by examining the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the added charge needed to swing the drain voltage of the power device as it switches between the ON and OFF states. Most manufacturers provide specifications of typical and maximum gate charge, in nC, to switch the device under specified conditions. Using the gate charge Qg, determine the power that must be dissipated when charging a capacitor. This is done by using the equation, Q_G = C_LOAD x V_DD, to provide Equation 4 for power:

Equation 4.

This power P_G is dissipated in the resistive elements of the circuit when the MOSFET/IGBT is being turned on or turned off. Half of the total power is dissipated when the load capacitor is charged during turnon, and the other half is dissipated when the load capacitor is discharged during turnoff. When no external gate resistor is employed between the driver and MOSFET/IGBT, this power is completely dissipated inside the driver package. With the use of external gate-drive resistors, the power dissipation is shared between the internal resistance of driver and external gate resistor in accordance to the ratio of the resistances (more power dissipated in the higher resistance component). Based on this simplified analysis, the driver power dissipation during switching is calculated in Equation 5.

Equation 5.

where

• R_OFF = R_OL
• R_ON (effective resistance of pullup structure) = 1.4 x R_OL