Table 2. UCC2751x Family of Features and Benefits

9.3.1 VDD and Undervoltage Lockout

The UCC2751x family of devices has internal undervoltage lockout (UVLO) protection feature on the VDD pin supply-circuit blocks. Whenever the driver is in UVLO condition (such as when V_DD voltage less than V_ON during power up and when V_DD voltage is less than V_OFF during power down), this circuit holds all outputs LOW, regardless of the status of the inputs. The UVLO is typically 4.2 V with 300-mV typical hysteresis. This hysteresis helps prevent chatter when low V_DD supply voltages have noise from the power supply and also when droops in the VDD bias voltage occur when the system commences switching and when a sudden increase in I_DD occurs. The capability to operate at low voltage levels such as below 5 V, along with best-in-class switching characteristics, is especially suited for driving emerging GaN wide bandgap power semiconductor devices.

For example, at power up, the UCC2751x driver output remains LOW until the V_DD voltage reaches the UVLO threshold. The magnitude of the OUT signal rises with V_DD until steady-state V_DD is reached. In the noninverting device (PWM signal applied to IN+ pin) shown in Figure 20, the output remains LOW until the UVLO threshold is reached, and then the output is in-phase with the input. In the inverting device (PWM signal applied to IN– pin) shown in Figure 21, the output remains LOW until the UVLO threshold is reached, and then the output is out-phase with the input.

Because the driver draws current from the VDD pin to bias all internal circuits, for the best high-speed circuit performance, two VDD bypass capacitors are recommended to prevent noise problems. The use of surface mount components is highly recommended. A 0.1-μF ceramic capacitor should be located as close as possible to the VDD to GND pins of the gate driver. In addition, a larger capacitor (such as 1 μF) with relatively low ESR should be connected in parallel and close proximity, to help deliver the high-current peaks required by the load. The parallel combination of capacitors should present a low impedance characteristic for the expected current levels and switching frequencies in the application.

Figure 20. Power-Up (Noninverting Drive)

Figure 21. Power-Up (Inverting Drive)

9.3.2 Operating Supply Current

The UCC2751xA-Q1 family of devices features very-low quiescent I_DD currents. The typical operating supply current in undervoltage lockout (UVLO) state and fully-on state (under static and switching conditions) are summarized in Figure 5, Figure 6 and Figure 7. The I_DD current when the device is fully on and outputs are in a static state (DC high or DC low, refer Figure 7) represents lowest quiescent I_DD current when all the internal logic circuits of the device are fully operational. The total supply current is the sum of the quiescent I_DD current, the average I_OUT current because of switching and finally any current related to pullup resistors on the unused input pin. For example when the inverting input pin is pulled low additional current is drawn from VDD supply through the pullup resistors (see the Functional Block Diagram section for the device block diagram). Knowing the operating frequency (f_SW) and the MOSFET gate (Q_G) charge at the drive voltage being used, the average I_OUT current can be calculated as product of Q_G and f_SW.

A complete characterization of the IDD current as a function of switching frequency at different VDD bias voltages under 1.8-nF switching load is provided in Figure 15. The strikingly linear variation and close correlation with theoretical value of average I_OUT indicates negligible shoot-through inside the gate-driver device attesting to its high-speed characteristics.

9.3.3 Input Stage

The input pins of UCC2751xA-Q1 family of devices are based on CMOS input logic where the threshold voltage level is a function of the bias voltage applied on the VDD pin. Typically, the Input high threshold (V_INH) is 55% VDD and input low threshold (VIN_L) is 39% VDD. Hysteresis (typically 19% VDD), which is available on the input threshold, offers noise immunity. With high VDD voltages resulting in wide hysteresis, slow dV/dt input signals are acceptable in the INx pins and RC circuits can be inserted between the input PWM signal and the INx pins of UCC2751xA-Q1 family of devices, to program a delay between the input signal and output transition.

The input pins have the ability to sustain negative voltages below the GND pin. This ability offers higher robustness and makes the design simpler when long traces are present between the PWM controller output and input of gate driver. An example of such a situation is when the controller is mounted on a daughter card and the gate driver is on the power stage board, close to the power switches.

9.3.4 Enable Function

The enable pin is based on a noninverting configuration (active high operation). When the EN pin is driven high the output is enabled and when the EN pin is driven low the output is disabled. Unlike input pin, the enable pin threshold is based on a TTL/CMOS-compatible input threshold logic that does not vary with the supply voltage. Typically, the enable high threshold (V_ENH) is 2.1 V and enable low threshold (VEN_L) is 1.25 V. Thus the EN pin can be effectively controlled using logic signals from 3.3-V and 5-V microcontrollers. The EN pin is internally pulled up to VDD using pullup resistor as a result of which the output of the device is enabled in the default state. Hence the EN pin can be left floating or not connected (NC) for standard operation, when enable feature is not needed. Essentially, this allows the UCC2751xA-Q1 family devices to be pin-to-pin compatible with TI’s previous generation drivers, the TPS2828-Q1 and TPS2829-Q1 device respectively, where pin number 1 is an NC pin. The enable pin also has the ability to sustain negative voltages below the GND pin.

9.3.5 Output Stage

The UCC2751xA-Q1 family of devices is capable of delivering 4-A source, 4-A sink (symmetrical drive) at VDD = 12 V. The output stage of the UCC2751xA-Q1 family of devices are shown in Figure 22. The UCC2751xA-Q1 family of devices features a unique architecture on the output stage which delivers the highest peak source current when it is most needed during the Miller plateau region of the power switch turn-on transition (when the power switch drain or collector voltage experiences dV/dt). The device output stage features a hybrid pullup structure using a parallel arrangement of N-channel and P-channel MOSFET devices. By turning on the N-channel MOSFET during a narrow instant when the output changes state from low to high, the gate-driver device is able to deliver a brief boost in the peak-sourcing current enabling fast turn on.

Figure 22. UCC2751xA-Q1 Gate Driver Output Structure

The R_OH parameter (see the Electrical Characteristics table) is a DC measurement and is representative of the on-resistance of the P-channel device only, because the N-channel device is turned on only during output change of state from low to high. Thus the effective resistance of the hybrid pullup stage is much lower than what is represented by R_OH parameter. The pulldown structure is composed of a N-channel MOSFET only. The R_OL parameter (see the Electrical Characteristics table), which is also a DC measurement, is representative of true impedance of the pulldown stage in the device. In the UCC2751xA-Q1 family of devices, the effective resistance of the hybrid pullup structure is approximately 1.4 × R_OL.

The driver output voltage swings between VDD and GND providing rail-to-rail operation, thanks to the MOS output stage which delivers very low dropout. The presence of the MOSFET body diodes also offers low impedance to switching overshoots and undershoots. This means that in many cases, external Schottky diode clamps may be eliminated. The outputs of these drivers are designed to withstand 500-mA reverse current without either damage to the device or logic malfunction.

9.3.6 Low Propagation Delays

The UCC2751xA-Q1 driver device features best-in-class input-to-output propagation delay of 17 ns (typical) at VDD = 12 V. This promises the lowest level of pulse transmission distortion available from industry standard gate driver devices for high-frequency switching applications. As shown in Figure 14, there is very little variation of the propagation delay with temperature and supply voltage as well, offering typically less than 20-ns propagation delays across the entire range of application conditions.

Table 3. Device Logic Table