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SLVSC90B August 2013 – August 2015 UCC27518A-Q1 , UCC27519A-Q1

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

DBV|5

散热焊盘机械数据 (封装 | 引脚)

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8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾⁽³⁾

		MIN	MAX	UNIT
Supply voltage	VDD	–0.3	20	V
OUTA, OUTB voltage	DC	–0.3	VDD + 0.3	V
OUTA, OUTB voltage	Repetitive pulse < 200 ns⁽⁵⁾	–2	VDD + 0.3	V
Output continuous current	I_{OUT_DC}(source/sink)		0.3	A
Output pulsed current (0.5 µs)	I_{OUT_pulsed} (source/sink)		4	A
IN+, IN–, EN⁽⁴⁾		–6	20	V
Operating virtual junction temperature, T_J		–40	150	°C
Lead temperature	Soldering, 10 s		300	°C
Lead temperature	Reflow		260	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See Packaging Section of the datasheet for thermal limitations and considerations of packages.

(3) These devices are sensitive to electrostatic discharge; follow proper device handling procedures.

(4) Maximum voltage on input pins is not restricted by the voltage on the VDD pin.

(5) Values are verified by characterization on bench

8.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾	±2500	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per AEC Q100-011	±1500	V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

	MIN	NOM	MAX	UNIT
Supply voltage, VDD	4.5	12	18	V
Input voltage, (IN+ and IN–) and enable (EN)	0		18	V
Operating ambient temperature	–40		140	°C

8.4 Thermal Information

THERMAL METRIC⁽¹⁾		UCC27518A-Q1 UCC27519A-Q1	UNIT
		DBV (SOT-23)
		5 PINS
R_θJA	Junction-to-ambient thermal resistance	215.5	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	136.1	°C/W
R_θJB	Junction-to-board thermal resistance	43.2	°C/W
ψ_JT	Junction-to-top characterization parameter	20.3	°C/W
ψ_JB	Junction-to-board characterization parameter	42.3	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

8.5 Electrical Characteristics

VDD = 12 V, T_A = –40°C to 140°C, 1-µF capacitor from VDD to GND. Currents are positive into, negative out of the specified terminal.

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
BIAS CURRENTS
I_DD(off)	Startup current	VDD = 3.4 V	IN+ = VDD (UC27519A-Q1) IN– = GND (UCC27518A-Q1)	51	85	123	µA
			IN– = VDD (UCC27518A-Q1)	51	70	103
			IN+ = GND (UC27519A-Q1)	51	70	110
UNDERVOLTAGE LOCKOUT (UVLO)
V_ON	Supply start threshold	T_A = 25°C		3.85	4.2	4.57	V
V_ON	Supply start threshold	T_A = –40°C to 140°C		3.8	4.2	4.67	V
V_OFF	Minimum operating voltage after supply start			3.45	3.9	4.35	V
V_{DD_H}	Supply voltage hysteresis			0.19	0.3	0.45	V
INPUTS (IN+, IN–)
V_{IN_H}	Input signal high threshold	VDD = 4.5 V			55	62	%VDD
V_{IN_L}	Input signal low threshold			31	39
V_{IN_HYS}	Input signal hysteresis				16
V_{IN_H}	Input signal high threshold	VDD = 12 V			55	59	%VDD
V_{IN_L}	Input signal low threshold			31	39
V_{IN_HYS}	Input signal hysteresis				16
V_{IN_H}	Input signal high threshold	VDD = 18 V			55	58	%VDD
V_{IN_L}	Input signal low threshold			35	38
V_{IN_HYS}	Input signal hysteresis				17
ENABLE (EN)
V_{EN_H}	Enable signal high threshold	VDD = 12 V			2.1	2.3	V
V_{EN_L}	Enable signal low threshold			1	1.25
V_{EN_HYS}	Enable hysteresis				0.86
SOURCE AND SINK CURRENT
I_SRC/SNK	Source/sink peak current⁽¹⁾	C_LOAD = 0.22 µF, F_SW = 1 kHz			±4		A
OUTPUTS (OUT)
V_DD–V_OH	High output voltage	VDD = 12 V I_OUT = –10 mA			50	90	mV
V_DD–V_OH	High output voltage	VDD = 4.5 V I_OUT = –10 mA			60	130	mV
V_OL	Low output voltage	VDD = 12 I_OUT = 10 mA			5	11	mV
V_OL	Low output voltage	VDD = 4.5 V I_OUT = 10 mA			6	12	mV
R_OH	Output pullup resistance⁽²⁾	VDD = 12 V I_OUT = –10 mA			5	7.5	Ω
R_OH	Output pullup resistance⁽²⁾	VDD = 4.5 V I_OUT = –10 mA			5.0	11	Ω
R_OL	Output pulldown resistance	VDD = 12 V I_OUT = 10 mA			0.5	1	Ω
R_OL	Output pulldown resistance	VDD = 4.5 V I_OUT = 10 mA			0.6	1.2	Ω

(1) Ensured by design.

(2) R_OH represents on-resistance of P-channel MOSFET in pullup structure of the output stage of the UCC27518A-Q1 and UCC27519A-Q1 device.

8.6 Switching Characteristics

VDD = 12 V, T_A = –40°C to 140°C, 1-µF capacitor from VDD to GND. Currents are positive into, negative out of the specified terminal. Over operating free-air temperature range (unless otherwise noted). See the timing diagrams in Figure 1, Figure 2, Figure 3, and Figure 4.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_R	Rise time	C_LOAD = 1.8 nF		8	12	ns
t_F	Fall time	C_LOAD = 1.8 nF		7	11	ns
t_D1	IN+ to output propagation delay	VDD = 10 V 7-V input pulse, C_LOAD = 1.8 nF	6	17	25	ns
t_D2	IN– to output propagation delay	VDD = 10 V 7-V input pulse, C_LOAD = 1.8 nF	6	17	24	ns
t_D3	EN to output high propagation delay	C_LOAD = 1.8 nF, 5-V enable pulse	4	12	16	ns
t_D4	EN to output low propagation delay	C_LOAD = 1.8 nF, 5-V enable pulse	4	12	19	ns