The UCC2752x devices have internal undervoltage-lockout (UVLO) protection feature on the V_DD pin supply circuit blocks. When V_DD is rising and the level is still below UVLO threshold, this circuit holds the output LOW, regardless of the status of the inputs. The UVLO is typically 4.2 V with 300-mV typical hysteresis. This hysteresis prevents chatter when low V_DD supply voltages have noise from the power supply and also when there are droops in the V_DD bias voltage when the system commences switching and there is a sudden increase in I_DD. The capability to operate at low voltage levels such as below 5 V, along with best-in-class switching characteristics, is especially suited for driving emerging GaN power semiconductor devices.

For example, at power up, the UCC2752x driver-device output remains LOW until the V_DD voltage reaches the UVLO threshold if Enable pin is active or floating. The magnitude of the OUT signal rises with V_DD until steady-state V_DD is reached. The non-inverting operation in Table 3-1 shows that the output remains LOW until the UVLO threshold is reached, and then the output is in-phase with the input. The inverting operation in Figure 7-5 shows that the output remains LOW until the UVLO threshold is reached, and then the output is out-phase with the input. With UCC27526 the output turns to high-state only if INX+ is high and INX– is low after the UVLO threshold is reached.

Because the device draws current from the V_DD pin to bias all internal circuits, for the best high-speed circuit performance, TI recommends two V_DD bypass capacitors to prevent noise problems. TI highly recommends using surface-mount components. A 0.1-μF ceramic capacitor must be located as close as possible to the V_DD to GND pins of the gate-driver device. In addition, a larger capacitor (such as 1-μF) with relatively low ESR must be connected in parallel and close proximity, in order to help deliver the high-current peaks required by the load. The parallel combination of capacitors presents a low impedance characteristic for the expected current levels and switching frequencies in the application.

Figure 7-4 Power up Non-Inverting Driver

Figure 7-5 Power up Inverting Driver