ZHCSGJ1 August   2017 UCC27712-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
      2.      典型传播延迟比较
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Dynamic Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD and Under Voltage Lockout
      2. 7.3.2 Input and Output Logic Table
      3. 7.3.3 Input Stage
      4. 7.3.4 Output Stage
      5. 7.3.5 Level Shift
      6. 7.3.6 Low Propagation Delays and Tightly Matched Outputs
      7. 7.3.7 Parasitic Diode Structure
    4. 7.4 Device Functional Modes
      1. 7.4.1 Minimum Input Pulse Operation
      2. 7.4.2 Output Interlock and Dead Time
      3. 7.4.3 Operation Under 100% Duty Cycle Condition
      4. 7.4.4 Operation Under Negative HS Voltage Condition
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Selecting HI and LI Low Pass Filter Components (RHI, RLI, CHI, CLI)
        2. 8.2.2.2 Selecting Bootstrap Capacitor (CBOOT)
        3. 8.2.2.3 Selecting VDD Bypass/Holdup Capacitor (CVDD) and Rbias
        4. 8.2.2.4 Selecting Bootstrap Resistor (RBOOT)
        5. 8.2.2.5 Selecting Gate Resistor RON/ROFF
        6. 8.2.2.6 Selecting Bootstrap Diode
        7. 8.2.2.7 Estimate the UCC27712-Q1 Power Losses (PUCC27712-Q1)
        8. 8.2.2.8 Estimating Junction Temperature
        9. 8.2.2.9 Operation With IGBT's
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 相关链接
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.5 Electrical Characteristics

At VDD = VHB = 15 V, COM = VHS = 0, all voltages are with respect to COM, no load on LO and HO, –40°C < TJ< +125°C (unless otherwise noted). Currents are positive into and negative out of the specified terminal.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY BLOCK
VVDD ON Turn-on threshold voltage of VDD 8.0 8.9 9.8 V
VVDD OFF Turn-off threshold voltage of VDD 7.5 8.4 9.3
VVDD HYS Hysteresis of VDD 0.5
VVHB ON Turn-on threshold voltage of VHB–VHS 7.2 8.2 9.2
VVHB OFF Turn-off threshold voltage of VHB–VHS 6.4 7.3 8.3
VVHB HYS Hysteresis of VHB–VHS 0.5 0.9
IQ Total quiescent supply current HI = LI = 0 V or 5 V, DC on/off state 180 255 420 µA
IQVDD Quiescent VDD-COM supply current HI = LI = 0 V or 5 V, DC on/off state 190 320
IQBS Quiescent HB-HS supply current HI = 0 V or 5 V, HO in DC on/off state 65 100
IBL Bootstrap supply leakage current HB = HS = 600 V 20
IOP Dynamic operating current HI = LI = 0 V or 5 V, f = 100 kHz, duty = 50%, CL= 1 nF 3800(1) 4500
INPUT BLOCK
VINH Input Pin (HI, LI) high threshold 1.6 2.0 2.4 V
VINL Input Pin (HI, LI) low threshold 0.8 1.2 1.5
VINHYS Input Pin (HI, LI) threshold hysteresis 0.8
IINL HI, LI input low bias current HI, LI = 0 V –5 0 5 µA
IINH HI, LI input high bias current HI, LI = 5 V 1.7 70
OUTPUT BLOCK
VDD-VLOH LO output high voltage LI = 5 V, ILO = –20 mA 60 136 mV
VHB-VHOH HO output high voltage HI = 5 V, IHO = –20 mA 60 136
VLOL LO output low voltage LI = 0 V, ILO = 20 mA 30 80
VHOL HO output low voltage HI = 0 V, IHO = 20 mA 30 80
RLOL, RHOL LO, HO output pull-down resistance ILO = IHO = 20 mA 1.5 4 Ω
RLOH, RHOH LO, HO output pull-up resistance ILO = IHO = –20 mA 3.0 6.8
IGPK-(1) HO, LO output low short circuit pulsed current HI = LI = 0 V, HO = LO = 15 V, PW < 10 µs 2.8 A
IGPK+(1) HO, LO output high short circuit pulsed current HI = LI = 5 V, HO = LO = 0 V, PW < 10 µs –1.8
(1) Ensured by design, not tested in production
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