A 1-V (typical) cycle-by-cycle current limit threshold is incorporated into the UCC280x family. Note that the 100-ns leading edge blanking pulse is applied to this current limiting circuitry. The blanking overrides the current limit comparator output to prevent the leading edge switch noise from triggering a current limit function. Propagation delay from the current limit comparator to the output is typically 70 ns. This high-speed path minimizes power semiconductor dissipation during an overload by abbreviating the ON time.

For increased efficiency in the current sense circuitry, the circuit shown in Figure 9-16 can be used. Resistors R_A and R_B bias the actual current sense resistor voltage up, allowing a small current sense amplitude to be used. This circuitry provides current limiting protection with lower power loss current sensing.

Figure 9-16 Biasing CS For Lower Current Sense Voltage

Figure 9-17 CS Pin Voltage with Biasing

The example shown uses a 200-mV full scale signal at the current sense resistor. Resistor R_B biases this up by approximately 700 mV to mate with the 0.9-V minimum specification of the current limit comparator of the IC. The value of resistor R_A changes with the specific IC used, due to the different reference voltages. The resistor values must be selected for minimal power loss. For example, a 50-µA bias sets R_B = 13 kΩ, R_A = 75 kΩ (UCCx800, UCC2801, UCC2802, and UCC2804), or R_A = 56 kΩ with the UCC2803 and UCC2805 devices.