12.1 Layout Guidelines

In addition to following general power management IC layout guidelines (star grounding, minimal current loops, reasonable impedance levels, and so on) layout for the UCC280x-Q1 family must consider the following:

• If possible, a ground plane must be used to minimize the voltage drop on the ground circuit and the noise introduced by parasitic inductances in individual traces.

• A decoupling capacitor is required for both the VCC pin and REF pin and both must be returned to GND as close to the IC as possible.

• For the best performance, keep the timing capacitor lead to GND as short and direct as possible. If possible, use separate ground traces for the timing capacitor and all other functions.

• The CS pin filter capacitor must be as close to the IC possible and grounded right at the IC ground pin. This ensures the best filtering effect and minimizes the chance of current sense pin malfunction.

• Gate driver loop area must be minimized to reduce the EMI noise because of the high di/dt current in the loop.