10.2.2.6.1 Power Stage Gain, Zeroes, and Poles

The first step in compensating a fixed frequency flyback is to verify if the converter is continuous conduction mode (CCM) or discontinuous conduction mode (DCM).  If the primary inductance, L_P, is greater than the inductance for DCM, CCM boundary mode operation, called the critical inductance, or L_Pcrit, then the converter operates in CCM calculated with Equation 20.

For the entire input voltage range, the selected inductor has value larger than the critical inductor. Therefore, the converter operates in CCM and the compensation loop requires design based on CCM flyback equations.

The current-to-voltage conversion is done externally with the ground-referenced current sense resistor, R_CS, and the internal resistor divider sets up the internal current sense gain, A_CS = 1.65.  The IC technology allows the tight control of the resistor divider ratio, regardless of the actual resistor value variations.

The DC open-loop gain, G_O, of the fixed-frequency voltage control loop of a peak current mode control CCM flyback converter shown in Figure 33 is approximated by first using the output load, R_OUT, the primary to secondary turns ratio, N_PS, the maximum duty cycle, D, calculated in Equation 21.

In Equation 21, D is calculated with Equation 22, τ_L is calculated with Equation 23, and M is calculated with Equation 24.

For this design, a converter with an output voltage V_OUT of 12 V, and 48 W relates to an output load, R_OUT, equal to 3 Ω at full load.

At minimum input voltage of 75 V DC, the duty cycle reaches it maximum value of 0.615. The current sense resistance, R_CS, is 0.75 Ω, and a primary to secondary turns-ratio, N_PS is 10. The open-loop gain calculates to 14.95 dB.

A CCM flyback has two zeroes that are of interest. The ESR and the output capacitance contribute a left-half plane zero to the power stage, and the frequency of this zero, f_ESRz, are calculated with Equation 25.

The f_ESRz zero for a capacitance bank of three 680-µF capacitors for a total output capacitance of 2040 µF and a total ESR of 13 mΩ is placed at 6 kHz.

CCM flyback converters have a zero in the right-half plane, RHP, in their transfer function. RHP zero has the same 20 dB/decade rising gain magnitude with increasing frequency just like a left-half plane zero, but it adds phase lag instead of lead. This phase lag tends to limit the overall loop bandwidth. The frequency location, f_RHPz in Equation 26, is a function of the output load, the duty cycle, the primary inductance, L_P, and the primary to secondary side turns ratio, N_PS.

Right half plane zero frequency increases with higher input voltage and lighter load. Generally, the design requires consideration of the worst case of the lowest right half plane zero frequency and the converter must be compensated at the minimum input and maximum load condition. With a primary inductance of 1.5 mH, at 75-V DC input, the RHP zero frequency, f_RHPz, is equal to 7.65 kHz at maximum duty cycle, full load.

The power stage has one dominate pole, ω_P1, which is in the region of interest, placed at a lower frequency, f_P1, which is related to the duty cycle, D, the output load, and the output capacitance. There is also a double pole placed at half the switching frequency of the converter, f_P2 calculated with Equation 27 and Equation 28.

Slope compensation is the large signal sub-harmonic instability that can occur with duty cycles that extends beyond 50%. The subharmonic oscillation increases the output voltage ripple and sometimes it even limits the power handling capability of the converter.

The target of slope compensation is to achieve idea quality coefficient, Q_p , at half of the switching frequency to be 1. The Q_p is calculated with Equation 29.

In Equation 29, D is the primary side switch duty cycle and M_C is the slope compensation factor, which is defined with Equation 30.

In Equation 30, Se is the compensation ramp slope and the S_n is the inductor rise slope. The optimal goal of the slope compensation is to achieve Q_P equal to 1, which mean M_C  must be 2.128 when D reaches it maximum value of 0.615.

The inductor rise slop on CS pin is calculated with Equation 31.

The compensation slope is calculated with Equation 32.

The compensation slope is added into the system through R_RAMP and R_CSF. The C_RAMP is selected to approximate high frequency short circuit. Choose C_RAMP as 10 nF as the starting point, and make adjustments if required. The R_RAMP and R_CSF forms a voltage divider from the RC pin ramp voltage and inject the slope compensation into CS pin. Choose R_RAMP much larger than the R_T resistor  so that it won’t affect much the frequency setting.  In this design, R_RAMP is selected as 24.9 kΩ. The RC pin ramp slope is calculated with Equation 33.

To achieve 46.3 mV/µs compensation slope, R_CSF resistor is calculated with Equation 34.

The power stage open-loop gain and phase can be plotted as a function of frequency. The total gain, as a function of frequency can be characterized with Equation 35.

The bode is plotted accordingly (see Figure 34 and Figure 35).