The IC receives all of its power through the VCC pin. This voltage should be as well regulated as possible through all of the operating conditions of the PFC stage. Consider creating the steady state bias for this stage from a downstream DC:DC stage which will in general be able to provide a bias winding with very well regulated voltage. This strategy will enhance the overall efficiency of the bias generation. A lower efficiency alternative will be to consider a series connected Fixed Positive Voltage Regulator such as the UA78L15A.

For all normal and abnormal operating conditions it is critically important that VCC remains within its Recommended Operating Range for both Voltage and Input Current. VCC overvoltage may cause excessive power dissipation in the internal voltage clamp and undervoltage may cause inadequate drive levels for power MOSFETs, UVLO events (causing interrupted PFC operation) or inadequate headroom for the various on-chip linear regulators and references.

Note also that the high RMS and peak currents required for the MOSFET gate drives are provided through the IC 13.5-V linear regulator, which does not have provision for the addition of external decoupling capacitance. For higher Powers, very high Q_G power MOSFETs or high switching frequencies, consider using external driver transistors, local to the power MOSFETs. These will reduce the IC operating temperature and ensure that the VCC maximum input current rating is not exceeded.

Use decoupling capacitances between VREF and AGND and between VCC and PGND which are as local as possible to the IC. These should have some ceramic capacitance which will provide very low ESR. PGND and AGND should ideally be star connected at the control IC so that there is negligible DC or high frequency AC voltage difference between PGND and AGND. Use values for decoupling capacitors similar to or a little larger than those used in the EVM.

Pay close attention to start-up and shutdown VCC bias bootstrap arrangements so that these provide adequate regulated bias power as early as possible during power application and as late as possible during power removal. Ensure that these start-up bias bootstrap circuits do not cause unnecessary steady-state power drain.