ZHCSIB2B December 2017 – October 2019 UCC28064A
PRODUCTION DATA.
- 1 特性
- 2 应用
- 3 说明
- 4 修订历史记录
- 5 说明 （续）
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Principles of Operation
- 8.3.2 Natural Interleaving
- 8.3.3 On-Time Control, Maximum Frequency Limiting, Restart Timer and Input Voltage Feed-Forward compensation
- 8.3.4 Distortion Reduction
- 8.3.5 Zero-Current Detection and Valley Switching
- 8.3.6 Phase Management and Light-Load Operation
- 8.3.7 Burst Mode Operation
- 8.3.8 External Disable
- 8.3.9 Improved Error Amplifier
- 8.3.10 Soft Start
- 8.3.11 Brownout Protection
- 8.3.12 Line Dropout Detection
- 8.3.13 VREF
- 8.3.14 VCC
- 8.3.15
System Level Protections
- 8.3.15.1 Failsafe OVP - Output Over-voltage Protection
- 8.3.15.2 Overcurrent Protection
- 8.3.15.3 Open-Loop Protection
- 8.3.15.4 VCC Undervoltage Lock-Out (UVLO) Protection
- 8.3.15.5 Phase-Fail Protection
- 8.3.15.6 CS - Open, TSET - Open and Short Protection
- 8.3.15.7 Thermal Shutdown Protection
- 8.3.15.8 Fault Logic Diagram
- 8.4 Device Functional Modes
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 Design Requirements
- 9.2.2
Detailed Design Procedure
- 9.2.2.1 Custom Design With WEBENCH® Tools
- 9.2.2.2 Inductor Selection
- 9.2.2.3 ZCD Resistor Selection RZA, RZB
- 9.2.2.4 HVSEN
- 9.2.2.5 Output Capacitor Selection
- 9.2.2.6 Selecting RS For Peak Current Limiting
- 9.2.2.7 Power Semiconductor Selection (Q1, Q2, D1, D2)
- 9.2.2.8 Brownout Protection
- 9.2.2.9 Converter Timing
- 9.2.2.10 Programming VOUT
- 9.2.2.11 Voltage Loop Compensation
- 9.2.3 Application Curves
- 10Power Supply Recommendations
- 11Layout
- 12Package Option Addendum
- 13器件和文档支持
- 14机械、封装和可订购信息
9.2.2.2 Inductor Selection
The boost inductor is selected based on the minimum switching requirements. Operating at the boundary between DCM and CCM the minimum switching frequency will be at maximum power and at the peak of the line. It is possible that the minimum switching frequency can occur at minimum line or at maximum line. Equation 20.
In order to be sure that converters operates always above the desired (fMIN) we will select the minimum value between LH that would be the value we have if we consider the minimum occurs at maximum input voltage and LL that would be the value we have if we consider that minimum switching frequency occurs at minimum Line voltage. For this design example, fMIN is set to 27 kHz in order to be always above the audible range. For a 2-phase interleaved design, L1 and L2 are determined by minimum between LH and LLas stated in formula (19) here belowEquation 21.
The inductor for this design would have a peak current (ILPEAK) of 5.4 A, as shown in Equation 22, and an RMS current (ILRMS) of 2.2 A, as shown in Equation 23.
This converter uses constant on time (TON) and zero-current detection (ZCD) to set up the converter timing. Auxiliary windings on L1 and L2 detect when the inductor currents are zero. Selecting the turns ratio using Equation 24 ensures that there will be at least 2 V at the peak of high line to reset the ZCD comparator after every switching cycle.
The turns-ratio of each auxiliary winding is:
