8.1.2.1 Secondary-Side Control

For secondary-side control, the UCC28250 implements close-loop control of both the primary-side switches and secondary-side synchronous rectifiers’ duty cycles. This makes it easy to achieve optimal start-up performance.

The internal error amplifier is set up as the control loop error amplifier. Connect REF/EA+, FB/EA-, COMP and VSENSE as shown in Figure 39. To achieve optimal prebiased start-up performance, the output voltage must be directly measured. The UCC28250 uses the VSENSE pin to directly sense this output voltage. Choose the voltage dividers on VSENSE slightly different to the FB/EA- voltage divider so that the voltage on VSENSE pin is roughly 10% to 15% more than FB/EA- pin voltages. Select R_O1 equal to R_S1, and R_S2 about 10% to 15% smaller than R_O2.

Figure 39. Error Amplifier Set Up for Secondary-Side Control

The error amplifier uses the lower voltage between the SS pin and the REF/EA+ pin to be the reference voltage for the feedback loop. In this method, the control loop is said to be ‘closed’ during the entire start-up process, as it is always based on the true output voltage.

During soft start, the primary-side switch duty cycle is controlled by the COMP pin voltage and ramp voltage generated on the RAMP/CS pin. A higher COMP pin voltage results in larger duty cycle. However, to improve start-up performance, the secondary-side synchronous rectifier duty cycle is controlled by a separate, internal ramp signal (generated by a dedicated prebiased start-up loop) and by the COMP pin voltage. This dedicated prebiased loop is much faster than the regular voltage loop to avoid interaction between the two loops. The start-up loop reads the output voltage through a transconductance error amplifier connected to the VSENSE pin. When the output voltage is higher than the reference, the prebiased start-up loop increases the SR duty cycle to reduce the output voltage. Conversely, when the output voltage is lower than the reference, the SR duty cycle is decreased to help maintain higher output voltage. To speed up the start-up time, the minimum duty cycle of the synchronous rectifier is 50%.

Once the soft start is finished, the prebiased loop is disabled and the duty cycle of the synchronous rectifiers becomes the complimentary of primary switches’ duty cycle, with some dead time inserted in between.

8.1.2.2 Primary-Side Control

When the UCC28250 is sitting on the primary side, the internal error amplifier is connected as a voltage follower and an extra error amplifier is needed on the secondary side for closed loop control. The error amplifier implementation is shown in Figure 40.

Figure 40. Error Amplifier Setup for Primary-Side Control

In the above configuration, the UCC28250 can only see the control loop feedback voltage, and cannot directly access the output voltage. The design of the soft-start time is critical to achieve optimal prebiased start-up performance. Some trial and error approaches are needed to achieve optimal performance. It is also important to choose the appropriate ramp amplitude. Refer to RAMP/CS (PWM Ramp Input or Current Sense Input) (16/3) discussion on the detailed design procedure for choosing ramp generation components.

During soft start, regardless of the prebiased condition, the output voltage is always lower than the regulation voltage, so that the feedback loop is always saturated. When the internal error amplifier is connected as a voltage follower, the COMP voltage follows the lower of the voltage on the RER/EA+ pin and the SS pin. Because the feedback loop is saturated, the COMP pin always follows the SS pin voltage, until the output voltage becomes regulated and the feedback voltage takes over. In this control method, the output voltage control loop is always saturated, and the controller soft starts the COMP pin voltage. Therefore, it is called open loop soft start.

The primary-side switch duty cycle is controlled by the COMP pin voltage and by the RAMP/CS pin voltage. During soft start, the COMP pin voltage follows the SS pin as it is rising, so the primary-side switch duty cycle keeps increasing. When the output voltage becomes regulated, the feedback voltage becomes less than the SS pin voltage and the primary-side switch comes controlled by the control loop.

For the primary-side control setup, because output voltage is not directly accessible, the internal prebiased start-up loop is disabled by connecting VSENSE to VREF. Instead, the internal ramp used to generate the synchronous rectifier duty cycle is fixed, with the peak voltage of 3 V. The duty cycle of the synchronous rectifier increases as the SS pin voltage increases. When the SS pin voltage reaches 2.9 V, the soft start is considered finished and the synchronous rectifier duty cycle becomes the complementary of the primary-side switch duty cycle, minus the programmed dead time. Because of different COMP pin voltages at different line voltages, the SR duty cycle generated by the internal ramp might be different than the complementary of the primary-side switch duty cycle (1-D). If the duty cycle is too large, the internal logic is able to limit the duty cycle to (1-D). However, if the duty cycle is too small, when the soft start is finished, the SR duty cycle has a sudden change, which will cause output voltage disturbance. To optimize the prebiased start-up performance, TI recommends that the duty cycle change at the end of soft start be as small as possible.

8.1.2.3 Voltage Mode Control and Input Voltage Feed-Forward

For voltage mode control, a resistor R_CS and a capacitor C_CS are connected externally at RAMP/CS pin as shown in Figure 41. A ramp signal is generated on the RAMP/CS pin, at a rate of two times that of the switching frequency. The generated ramp signal is used to control the duty cycle for both the primary-side switches and secondary-side synchronous rectifiers. The ramp amplitude can be fixed or variable with the input voltage (input voltage feedforward).

To realize a fixed amplitude ramp, connect R_CS to the VREF pin, so that the ramp capacitor charging voltage is fixed regardless of line and load condition. The RAMP/CS pin is clamped internally to 4 V for internal device protection. Because the internal pulldown switch has about 40-Ω on-resistance, the C_CS value must be small enough to discharge RAMP/CS from the peak to ground within T_D(sp) + 70 ns (that is, the pulse width of BLANK signal).

To achieve the input voltage feedforward, the slope of the ramp must be proportional to the input voltage. Tie R_CS to the input line voltage. Because the ramp voltage is much lower than the input voltage, the ramp capacitor charging current is considered to be proportional to the input voltage. With input voltage feedforward, the COMP pin voltage should only move slightly even with large input voltage variation. This will provide much better line transient response for the converter.

Figure 41. External Configuration of RAMP/CS Pin With/Without Feed-Forward Operation

The input voltage feedforward also helps on prebiased start-up. When doing primary-side control to prebiased start-up, three conditions need to be considered:

8.1.2.3.2 Condition 2

At the end of soft start, it is required to keep the SR duty cycle change to be as small as possible. With input voltage feedforward, the COMP pin voltage is virtually fixed for different input voltages. Therefore, before the end of soft start, the duty cycle is the same for different input voltages. Choose the R_CS and C_CS following the procedure.

Considering initial start-up, the RAMP peak voltage should be:

Equation 23.

In this equation, VIN is the input voltage because of the feedforward any input voltage should be fine; V_PRE-BIAS is the highest prebias start-up voltage required by the system; n is the tranformer primary to secondary turns ratio and V_SR(ramp) is the internal SR ramp peak voltage 3 V.

Another consideration is at the end of soft start, the SR duty cycle changes from controlled by the soft start, to complimentary to the primary-side duty cycle. The design should keep the transition as smooth as possible. Considering this, based on the output voltage and input voltage range, as well as the transformer turns ratio, calculate the SR duty cycle at different line voltages.

Next, based on the maximum duty cycle on the SR_D_MAX, and the internal fixed ramp amplitude 3 V, the COMP voltage at regulation can be chosen as:

Equation 24.

8.1.2.3.3 Condition 3

Use the calculated COMP pin voltage to derive the external ramp amplitude

Equation 25.

According to the calculated ramp voltage from Equation 23 and Equation 25 some trade off is required to pick up the appropriate ramp voltage. Based on the selected ramp capacitor C_CS value, choose the ramp resistor R_CS value:

Equation 26.

In this equation, V_IN(max) is the maximum input voltage, f_SW is the switching frequency.

Because these calculations ignore the dead time and the non-linearity of the ramp, slight modification is expected to achieve the optimal design. When the input voltage feed forward is not used, refer to RAMP/CS (PWM Ramp Input or Current Sense Input) (16/3) for RC calculation.

8.1.2.4 Peak Current Mode Control

For peak current mode control, RAMP/CS pin is connected directly with the current signal generated from a current transformer. The current signal must be compatible with the input range of the COMP pin. External slope compensation is required to prevent sub-harmonic oscillation and to maintain flux-balance. The slope compensation can be implemented by using OUTA and OUTB to charge external capacitors and use the voltage follower to add into the sensed the current signal, as shown in Figure 42. Follow the peak current mode control theory to select compensation slope or refer to Modeling, Analysis and Compensation of the Current-Mode Converter, (SLUA101).

Figure 42. UCC28250 Set Up for Peak Current Mode Control

8.1.2.5 Cycle-by-Cycle Current Limit and Hiccup Mode Protection

Cycle-by-cycle current limit is accomplished using the ILIM pin for both current mode control and voltage mode control. The input to the ILIM pin represents the primary current information. If the voltage sensed at ILIM pin exceeds 0.5 V, the current sense comparator terminates the pulse of output OUTA or OUTB. If the high current condition persists, the controller operates in a cycle-by-cycle current limit mode with duty cycle determined by the current sense comparator instead of the PWM comparator. ILIM pin is pulled down by an internal switch at the rising edge of each clock cycle. This internal switch remains on for an additional 70 ns after OUTA or OUTB goes high to blank leading edge transient noise in the current sensing loop. This reduces the filtering requirements at the ILIM pin and improves the current sense response time.

UCC28250 makes it possible to maintain flux balance during cycle-by-cycle current limit operation. The duty cycles of primary switches are always matched. If one switch duty cycle is terminated earlier because of current limiting, a matched duty cycle is applied to the other switch for the next half switching cycle, regardless of the current condition, as shown in Figure 43. This matched duty cycle helps to maintain volt-second balancing on the transformer and prevents the transformer saturation.

Figure 43. Cycle-by-Cycle Current Limit Duty Cycle Matching

Once the current limit is triggered, the 75-µA internal current source begins to charge the capacitor on HICC pin. If the current limit condition went away before HICC pin reaches 0.6 V, the device stops charge HICC capacitor and begins to discharge it with 2.7-µA current source. If the cycle-by-cycle current limit condition continues, HICC pin reachs 0.6 V, and all four outputs are shut down. The UCC28250 then enters hiccup mode. During hiccup mode, all four outputs keep low; SS pin is pulled to ground internally; a 2.7-µA current source continuously discharge HICC pin capacitor; until HICC pin voltage reaches 0.3 V. After that, HICC pin is discharged internally to get ready for the next HICC event. The whole converter starts with soft start after hiccup mode.

The cycle-by-cycle current limit operation time before all four outputs shut down is programmed by external capacitor C_HICC at HICC pin. The delay time can be calculated as:

Equation 27.

The hiccup timer keeps all outputs being zero until the timer expires. The hiccup time T_HICC is calculated as:

Equation 28.

As soon as the outputs are shut-down, SS pin is pulled down internally until the hiccup restart timer is reset after time duration T_HICC. The detailed illustration of HICCUP mode is shown in Figure 44.

Figure 44. Cycle-by-Cycle Current Limit Delay Timer and Hiccup Restart Timer

8.2.1.1 Design Requirements

Table 1 shows the specifications for the design example.

8.2.1.2 Detailed Design Procedure

8.2.1.2.3 Step 3, Programming the Device

8.2.1.2.3.1 Step 3-1

Equation 3 is used to determine RT based on switching frequency, 300 kHz and assumes the dead time of 150 ns.

Equation 29.

8.2.1.2.3.2 Step 3-2, Determine RAMP Resistance and Capacitance

There are two-fold considerations to determine RAMP resistance and capacitance. Equation 23 provides RAMP consideration for SR initial start-up with prebias. The corresponding RAMP peak voltage is determined with input voltage low line and maximum prebias output voltage. In the following, T1 turns ratio n = 4.

Equation 30.

Equation 24 and Equation 25 provides RAMP consideration for soft start completion to make duty cycle match (1-D) = SR_D.

1. Calculate OUTA or OUTB duty cycle at 75-V input voltage, 3.3-V output.
Equation 31.
2. Calculate SRA or SRB duty cycle.
Equation 32.
3. Calculate the COMP voltage value in steady state (Equation 24).
Equation 33.
4. Calculate the RAMP peak value (Equation 25).
Equation 34.
5. Arbitrary select C_RAMP 470 pF, then C3 = 470 pF.
6. Calculate R_RAMP.
Equation 35.
Equation 36.

As different RAMP resistor values are obtained, at this stage, we may take their average value for initial design.

8.2.1.2.4 Step 3-3, Determine Soft-Start Capacitance

Determine soft-start capacitance with soft-start time 15 ms.

Equation 37.

8.2.1.2.6 Step 3-5, Determine OCP Hiccup Off-Time Capacitance

Assuming off time is 0.8 s (Equation 15).

Equation 38.

8.2.1.2.7 Step 3-6, Determine Primary-Side OVP Resistance

Assuming OV_OFF = 73 V, OV_ON = 72 V (Equation 16 to Equation 18).

Equation 39.

Equation 40.

Equation 41.

8.2.1.2.8 Step 3-7, Select Capacitance for VDD and VREF

As recommended by the data sheet, select C6 = C4 = 1 µF. The final design is shown in Figure 46.

Figure 46. Schematics of Primary-Side Control Design Example

8.2.1.3 Application Curves

Figure 47. Load Transient

Figure 49. Clock Signal and Switching Node Waveform

Figure 51. Enable Turnoff Waveform

Figure 48. Output Ripple

Figure 50. Enable Turnon Waveform

Figure 52. Secondary-Side Switching Waveform