10.1 Layout Guidelines

To increase the reliability and robustness of the design, the following layout guidelines must be met.

1. REF/EA+ The REF/EA+ pin is the noninverting input of the error amplifier. For secondary side control, this pin is used to set the reference of voltage loop which decides the output voltage. So it is important to keep it clear from any of high voltage switching nodes. In addition, a decoupling capacitor located closely is recommended. For primary side control, this pin must be connected to opto-coupler. it is important minimize the loop area by running the EA+ signal and GND trace in parallel.
2. FB/EA- Minimize the loop between FB/EA- and COMP and keep it clear from any of high voltage switch nodes to avoid the noise injection into to the compensation loop.
3. COMP Minimize the loop between FB/EA- and COMP and keep it clear from any of high voltage switch nodes to avoid the noise injection into to the compensation loop.
4. GND As with all PWM controllers, the effectiveness of the filter capacitors on the signal pins depends upon the integrity of the ground return. Place all decoupling and filter capacitors as close as possible to the device pins with short traces. The AGND pin is used as the return connection for the low-power signaling and sensitive signal so it should be separated from the power stage ground to avoid ground bouncing.
5. VDD, VREF The VCC pin must be decoupled to GND by minimum 1-μF ceramic capacitors placed close to the pins.
6. SRA, SRB, OUTA, OUTB The SRA and SRB gate drive pins can be used to drive the inputs of gate driver or to directly drive the primary winding of a gate-drive transformer or the to directly drive the input of isolator. The tracks connected to these pins carry high dv/dt signals. Minimize noise pickup by routing them as far away as possible from tracks connected to sensitive signal including EA+, EA-, COMP, VSENSE, RT, RAMP/CS, ILIM, PS, SP.
7. HICC, SS, EN, OVP/OTP The connection track between the pin and external corresponding capacitor should be short.
8. PS, SP, RT, VSENSE, RAMP/CS, ILIM These pins are noise sensitive so allocate the related resistor as close as possible with the good ground connection.

10.2 Layout Example

Figure 54. Layout Example

10.3 Thermal Protection

Internal thermal shutdown circuitry protects the UCC28250 in the event the maximum rated junction temperature is exceeded. When activated, typically at 160°C, with the maximum threshold at 170°C and minimum threshold at 150°C the controller is forced into a low power standby mode. The outputs (OUTA, OUTB, SRA, SRB) are disabled. This helps to prevent accidental device overheating. A 20°C hysteresis is added to prevent comparator oscillation. During thermal shutdown, the UCC28250 follows a normal start-up sequence after the junction temperature falls below 140°C (typical value, with 130°C minimum threshold and 150°C maximum threshold).