7.3.1 Fault Recovery

The UCC28610 reacts with the programmed overload response if the overload lasts longer than t_OL (nominally 250 ms). The overload fault responses are either (1) latch-off or (2) shutdown/retry after a retry delay of 750 ms. The overload response is programmed with the MOT pin. The forced DCM feature prevents transformer saturation and limits the average and RMS output currents of the secondary winding of the transformer. Even under short circuit load conditions, the output current of the transformer is limited to the levels that are shown in Equation 1, where N_PS is the primary-to-secondary turns ratio. Typical behavior for a shorted load is shown in Figure 18.

Equation 1.

In shutdown/retry mode switching will be re-enabled after the 750-ms retry delay. In latch-off mode, a 7.5-kΩ load is activated at the DRV pin upon the activation by a fault condition. The internal 7.5-kΩ load draws current from the bulk capacitor through the HVMOSFET and the transformer primary winding. The bias voltage, VDD, is also regulated by the HVMOSFET during the latch-off state. Once the AC line is removed, a 2.8-mA current, I_DRV,DSCH, will discharge the bulk capacitor. Ultimately, VDD will discharge when the bulk voltage becomes sufficiently low. A normal start-up cycle can occur if the input voltage is applied after VDD falls below the fault reset level, VDD_{(FAULT RESET)}, which is approximately equal to 6 V.

Figure 18. Overload Behavior with a Shorted Output

7.3.2 Maximum On-Time and Brown Out

The forced DCM feature provides protection against excessive primary currents in the event that the input voltage becomes very low. The highest possible secondary currents can be described by Equation 1. The UCC28610 adds further protection by allowing the user to program the maximum on-time.

The Maximum On-Time (MOT) function causes the converter to react as if there is an overload condition if the load is sufficiently large during a line sag condition. During low line conditions the MOT function limits the on-time of the primary switch which limits the peak current in the primary power stage. Figure 19 shows how the MOT period, t_MOT, is programmed over the range of 1.5 μs to 5 μs for either range of programming resistors. The resistor range determines the controller’s response to a sustained overload fault – to either Latch-off or to Shutdown/Retry, which is the same response for a line-sag, or brown out, condition.

7.3.3 External Shutdown Using the MOT Pin

Many applications require the ability to shutdown the power supply with external means. This feature is easily implemented by connecting the collector and emitter of an NPN transistor between MOT and GND, respectively. The NPN transistor can be the photo-transistor of an opto-isolator for isolated applications.

Figure 19. Programming MOT and Overload Fault Response

For latch-off response to over-current or brownout:

Equation 2.

where:

Equation 3.

For shut-down/retry response to over-current or brownout:

Equation 4.

where:

Equation 5.

7.3.4 Overvoltage Detection

The UCC28610 controller monitors the output voltage by sampling the voltage at the auxiliary winding. The sampling time has a fixed delay of 1 μs, t_BLANK,OVP, after the internal driver turns off. This allows the auxiliary winding to be sampled after the bias winding voltage settles from the transient. This same delay is used to blank the ZCD input to avoid unintended zero crossing detection should the ringing be large enough to cross the ZCD zero crossing threshold.

The output over-voltage (OV) threshold is set using the turn ratio of the auxiliary winding to the output secondary and a resistive divider into the ZCD input pin. The UCC28610 will always enter a latched-off state if it detects an OV condition. The VDD supply must cycle below the fault reset threshold to re-start in order to recover. The functionality of the over-voltage detection function is shown in Figure 20.

Figure 20. Output Over-Voltage Protection with ZCD Pin

7.3.5 Solving for High Frequency Ringing

Cascode drive circuits are well known for high speed voltage gain. This topology can have small signal bandwidth well over 100 MHz and it can exhibit high frequency ringing. The internal HS Drive MOSFET shorts the gate to source of the external HVMOSFET during the turn-off interval of the switch cycle. This prevents the HVMOSFET from undesirably exciting the LC resonant circuit in the converter (the magnetizing inductance of the transformer and the stray drain capacitance). High frequency ringing can appear within the built-in dead-time between the turn-off of DRV and the turn-on of the HS Drive. A large amount of energy is transferred through the power components during this dead-time. Excessive high frequency ringing can cause EMI problems and become destructive in some situations.

7.3.5.2 Avoid HF Ringing

High frequency ringing problems with cascode MOSFET drives can often be avoided. Many converters will not have this problem because they use an HVMOSFET with a large V_th, large R_DS(on), low transconductance gain, or operate at low current. Ringing problems can also be avoided by minimizing stray inductance. The trace between the HVMOSFET source and the DRV pin must be kept very short, less than 1 cm. Do not add current probe loops to the source lead of the HVMOSFET. Do not place ferrite beads on the source lead of the HVMOSFET.

If ringing cannot be avoided, the most efficient and effective methods to solve ringing during switching transients are:

1. A ferrite chip or bead connected to the gate of the HVMOSFET,
2. A small capacitor connected from DRV to GND and
3. A gate turn-off resistor. These three techniques can be used separately or combined, as shown in Figure 21.

Figure 21. High Frequency Ringing Solutions, (a) ferrite chip, (b) CDRV and (c) RG-OFF

7.3.6 Thermal Shutdown

The UCC28610 protects itself from overheating with an internal thermal shutdown circuit. If the junction temperature exceeds the thermal shutdown point, T_SD, the UCC28610 initiates a shutdown event and permits retry after the retry time, t_RETRY. Shutdown/Retry cycles continue if the junction temperature is not less than T_SD minus T_{SD_HYST}.