8.3.2 AC Input UVLO / Brownout Protection

At start-up, once the VDD pin has reached the V_DD(start) level, the internal start-up current source is turned off. The controller tests the voltage across the bulk capacitor to determine if the level is high enough to allow the power stage to start, if it has exceeded the rising AC_ON level. Because there is no load across the bulk capacitor at this stage, the bulk voltage can be used as a proxy for the peak of the AC line. In order to measure the bulk voltage in a low-loss fashion, the controller generates a sequence of three exploratory switching pulses at a frequency of f_SW(uv), at minimum peak-current demand level V_CS(min) to avoid audible noise, and to deliver minimum energy to the output of the power stage.

Based on the magnetic sampling information determined via the bias winding during these switching pulses, if the output voltage is greater than the output overvoltage threshold, the pulsing stops immediately, and the controller transitions into latched-fault mode. If, however, there is no overvoltage condition detected at the output, the pulse-set completes. If the sensed line voltage is above the line AC_ON start threshold, then the controller starts up normally, and begins to generate the PWM drive pulses that charge and regulate the output voltage. Alternatively, if the sensed bulk level is below the AC_ON threshold, then the controller enters low power mode for the reset period (t_RESET(short)). It then depletes the VDD rail to the V_DD(reset) level. At this point, the start-up sequence repeats, and the device generates another set of exploratory switching pulses. This sequence repeats indefinitely until the AC input is increased to a sufficient level that the bulk voltage exceeds the AC_ON level.

Figure 17. AC Input UVLO Detection and Start Up

Once started, the controller regularly monitors the bulk capacitor voltage. Because the ripple on the bulk capacitor depends on the load level, the device determines the maximum bulk level every 11 ms (approprite for minimum AC frequency of 47 Hz), so the AC peak can be determined. The controller provides input undervoltage protection based on the sensed AC peak level. Once the peak drops below the AC_OFF level for the delay period (t_UV(delay)), the PWM switching halts, and the controller enters low-power mode for the reset period (t_RESET(short)). The device then discharges the bias voltage to the V_DD(reset) level, followed by a restart sequence. The controller cycles through the AC_ON, monitoring (detailed above) indefinitely until the AC input again rises above the AC_ON level.