10.1 Layout Guidelines

• High frequency bypass Capacitor C5 must be placed across Pin 1 and 4 as close as you can get it to the pins.
• Resistor R4 and C5 form a low pass filter and the connection of R4 and C5 must be as close to the VDD pin as possible.
• The VS pin controls the output voltage through the transformer turns ratio and the voltage divider of R5 and R11. Note the trace length between the R5, R11 and VS pin should be as short as possible to reduce or eliminate possible EMI coupling.
• The IC ground and power ground must meet at the bulk capacitor’s (C6 and C7) return. Try to ensure that high frequency/high current from the power stage does not go through the signal ground.
  • o The high frequency/high current path that you need to be cautious of on the primary is C7 +, T1 (P5, P3), Q1d, Q1s, R8 to the return of C6 and C7. Try to keep all high current loops as short as possible.
• Try to keep all high current loops as short as possible.
• Keep all high current/high frequency traces away from or perpendicular to other traces in the design.
• Traces on the voltage clamp formed by D1, R2, D3 and C2 as short as possible.
• C6 return needs to be as close to the bulk capacitor supply as possible. This reduces the magnitude of dv/dt caused by large di/dt.
• Avoid mounting semiconductors under magnetics.

10.2 Layout Example

Figure 29. Layout

Figure 30. 5W USB Adapter Schematic