7.3.1 Device Bias Voltage Supply (VDD)

The VDD pin is connected to a bypass capacitor to ground. The VDD turnon UVLO threshold is 21 V and turnoff UVLO threshold is 7.7 V, with an available operating range up to 35 V on VDD. The USB charging specification requires the output current to operate in constant-current mode from 5 V to a minimum of 2 V, which is easily achieved with a nominal VDD of approximately 22 V. The additional VDD headroom (up to 35 V) allows for VDD to rise due to the leakage energy delivered to the VDD capacitor in high-load conditions.

7.3.2 Ground (GND)

There is one ground reference external to the device for the base drive current and analog signal reference. TI recommends placing the VDD bypass capacitor close to GND and VDD with short traces to minimize noise on the VS and CS signal pins.

7.3.3 Voltage-Sense (VS)

The VS pin is connected to a resistor divider from the auxiliary winding to ground. The output-voltage feedback information is sampled at the end of the transformer secondary current demagnetization time to provide an accurate representation of the output voltage. Timing information for achieving valley-switching and to control the duty cycle of the secondary transformer current is determined by the waveform on the VS pin. Avoid placing a filter capacitor on this input because it would interfere with accurate sensing of this waveform.

The VS pin also senses the bulk capacitor voltage to provide for AC-input run and stop thresholds, and to compensate the current-sense threshold across the AC-input range. During the transistor on-time, the VS pin is clamped to approximately 250 mV below GND and the current out of the VS pin is sensed. For the AC-input run and stop function, the run threshold on VS is 225 µA and the stop threshold is 80 µA. The values for the auxiliary voltage divider upper-resistor (R_S1) and lower-resistor (R_S2) can be determined by Equation 1 and Equation 2.

Equation 1.

where

• N_PA is the transformer primary-to-auxiliary turns ratio.
• V_IN(run) is the AC RMS voltage to enable turnon of the controller (run).
• I_VSL(run) is the run-threshold for the current pulled out of the VS pin during the switch on-time (see Electrical Characteristics).

Equation 2.

where

• V_OCV is the converter regulated output voltage.
• V_F is the output rectifier forward drop at near-zero current.
• N_AS is the transformer auxiliary to secondary turns ratio.
• R_S1 is the VS divider high-side resistance.
• V_VSR is the CV regulating level at the VS input (see Electrical Characteristics).

7.3.4 Base Drive (DRV)

The DRV pin is connected to the NPN transistor base pin. The driver provides a base drive signal limited to 7 V. The turn-on characteristic of the driver is a 19-mA to 37-mA current source that is scaled with the current sense threshold dictated by the operating point in the control scheme. When the minimum current sense threshold is being used, the base drive current is also at its minimum value. As the current sense threshold is increased to the maximum, the base drive current scales linearly to its maximum of 35-mA typical. The turn-off current is determined by the low-side driver R_DS(on).

7.3.5 Current Sense (CS)

The current-sense pin is connected through a series resistor (R_LC) to the current-sense resistor (R_CS). The current-sense threshold is 0.78 V for I_PP(max) and 0.19 V for I_PP(min). The series resistor R_LC provides the function of feedforward line compensation to eliminate change in I_PP due to change in di/dt and the propagation delay of the internal comparator and NPN transistor turn-off time. There is an internal leading-edge blanking time of approximately 300 ns to eliminate sensitivity to the turnon current spike. It should not be necessary to place a bypass capacitor on the CS pin. The value of R_CS is determined by the target output current in constant current (CC) regulation. The values of R_CS and R_LC can be determined by Equation 3 and Equation 4. The term η_XFMR is intended to account for the energy stored in the transformer but not delivered to the secondary, which includes transformer resistance and core loss, bias power, and primary-to-secondary leakage ratio.

Equation 3.

where

• V_CCR is a current regulation constant (see Electrical Characteristics).
• N_PS is the transformer primary-to-secondary turns ratio (a ratio of 13 to 15 is recommended for 5-V output).
• I_OCC is the target output current in constant-current regulation.
• η_XFMR is the transformer efficiency.

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Equation 4.

where

• R_S1 is the VS pin high-side resistor value.
• R_CS is the current-sense resistor value.
• t _D is the current-sense delay including NPN transistor turn-off delay, add approximately 50 ns to transistor delay.
• N_PA is the transformer primary-to-auxiliary turns ratio.
• L_P is the transformer primary inductance.
• K_LC is a current-scaling constant (see Electrical Characteristics).

7.3.6 Cable Compensation (CBC)

The cable compensation pin is connected to a resistor to ground to program the amount of output voltage compensation to offset cable resistance. The cable compensation block provides a 0-V to 3-V voltage level on the CBC pin corresponding to I_OCC(max) output current. Connecting a resistance from CBC to GND programs a current that is summed into the VS feedback divider, increasing the regulation voltage as I_OUT increases. There is an internal series resistance of 28 kΩ to the CBC pin that sets a maximum cable compensation of a 5-V output to 400 mV when CBC is shorted to ground. The CBC resistance value can be determined by Equation 5.

Equation 5.

where

• V_OCV is the regulated output voltage.
• V_F is the diode forward voltage in V.
• V_OCBC is the target cable compensation voltage at the output terminals.
• V_CBC(max) is the maximum voltage at the cable compensation pin at the maximum converter output current (see Electrical Characteristics).
• V_VSR is the CV regulating level at the VS input (see Electrical Characteristics).

7.4.1 Primary-Side Voltage Regulation

Figure 12 illustrates a simplified flyback convertor with the main voltage regulation blocks of the device shown. The power train operation is the same as any DCM flyback circuit but accurate output voltage and current sensing is the key to primary-side control.

The main voltage regulation blocks are shown.

Figure 12. Simplified Flyback Convertor

In primary-side control, the output voltage is sensed on the auxiliary winding during the transfer of transformer energy to the secondary. As shown in Figure 13, it is clear there is a down slope representing a decreasing total rectifier (V_F) and resistance voltage drop (I_SR_S) as the secondary current decreases to zero. To achieve an accurate representation of the secondary output voltage on the auxiliary winding, ensure that the discrimantor:

• Reliably recognizes the leakage inductance reset, ringing, and ingores
• Continuously samples the auxiliary voltage during the down slope after the ringing is diminished
• Captures the error signal at the time the secondary winding reaches zero current

The internal reference on VS is 4.05 V. Temperature compensation on the VS reference voltage of –0.8-mV/°C offsets the change in the output rectifier forward voltage with temperature. The resistor divider is selected as outlined in the VS pin description.

Figure 13. Auxiliary Winding Voltage

The UCC28722 includes a VS signal sampler that uses discrimination methods to ensure an accurate sample of the output voltage from the auxiliary winding. There are some conditions that must be met on the auxiliary winding signal to ensure reliable operation. These conditions are the reset time of the leakage inductance and the duration of any subsequent leakage inductance ring. Refer to Figure 14 for a detailed illustration of waveform criteria to ensure a reliable sample on the VS pin. The first detail to examine is the duration of the leakage inductance reset pedestal, t_{LK_RESET} in Figure 14. Because this can mimic the waveform of the secondary current decay followed by a sharp downslope, it is important to keep the leakage reset time less than 600 ns for I_PRI minimum, and less than 2.2 µs for I_PRI maximum. The second detail is the amplitude of ringing on the V_AUX waveform following t_{LK_RESET}. The peak-to-peak voltage at the VS pin should be less than approximately 100 mV_p-p at least 200 ns before the end of the demagnetization time, t_DM. If there is a concern with excessive ringing, it usually occurs during light or no-load conditions, when t_DM is at the minimum. The tolerable ripple on VS scales up when measured at the auxiliary winding by R_S1 and R_S2, and is equal to 100 mV × (R_S1 + R_S2) / R_S2 when measured directly at the auxiliary winding.

Figure 14. Auxiliary Waveform Details

During voltage regulation, the controller operates in frequency modulation mode and amplitude modulation mode as illustrated in Figure 15. The internal operating frequency limits of the device are 80 kHz, f_SW(max) and 650 Hz, f_SW(min). The transformer primary inductance and primary peak current chosen sets the maximum operating frequency of the converter. The output preload resistor and efficiency at low power determines the converter minimum operating frequency. There is no stability compensation required for the UCC28722.

Figure 15. Frequency and Amplitude Modulation Modes During Voltage Regulation

7.4.2 Primary-Side Current Regulation

Timing information at the VS pin and current information at the CS pin allow accurate regulation of the secondary average current. The control law dictates that as power is increased in CV regulation and approaching CC regulation the primary-peak current is at I_PP(max). Referring to Figure 16, the primary-peak current, turns ratio, secondary demagnetization time (t_DM), and switching period (t_SW) determine the secondary average output current. Ignoring leakage inductance effects, the average output current is given by Equation 6. When the average output current reaches the regulation reference in the current control block, the controller operates in frequency modulation mode to control the output current at any output voltage at or below the voltage regulation target as long as the auxiliary winding can keep VDD above the UVLO turnoff threshold.

Figure 16. Transformer Currents

Equation 6.

Figure 17. Typical Target Output V-I Characteristic

7.4.3 Valley Switching

The UCC28722 utilizes valley switching to reduce switching losses in the transistor, to reduce induced-EMI, and to minimize the turnon current spike at the sense resistor. The controller operates in valley-switching in all load conditions unless the collector voltage (V_C) ringing has subsided.

Referring to Figure 18, the UCC28722 operates in a valley-skipping mode in most load conditions to maintain an accurate voltage or current regulation point and still switch on the lowest available V_C.

Figure 18. Valley-Skipping Mode

7.4.4 Start-Up Operation

An external resistor connected from the bulk capacitor voltage (V_BLK) to the VDD pin charges the VDD capacitor. The amount of startup current that is available to charge the VDD capacitor is dependent on the value of this external startup resistor. Larger values supply less current and increase startup time but at the expense of increasing standby power and decreasing efficiency at high input voltage and light loading. When VDD reaches the 21-V UVLO turnon threshold, the controller is enabled, the converter starts switching. The initial three cycles are limited to I_PP(min). After the initial three cycles at minimum I_PP(min), the controller responds to the condition dictated by the control law. The converter will remain in discontinuous mode during charging of the output capacitors, maintaining a constant output current until the output voltage is in regulation.

7.4.5 Fault Protection

The UCC28722 provides comprehensive fault protection. Protection functions include the following:

• Output over-voltage fault
• Input under-voltage fault
• Internal over-temperature fault
• Primary over-current fault
• CS pin fault
• VS pin fault

A UVLO reset and restart sequence applies for all fault protection events.

The output over-voltage function is determined by the voltage feedback on the VS pin. If the voltage sample on VS exceeds 115% of the nominal V_OUT, the device stops switching and the internal current consumption is I_FAULT which discharges the VDD capacitor to the UVLO turnoff threshold. After that, the device returns to the start state and a start-up sequence ensues.

The UCC28722 always operates with cycle-by-cycle primary peak current control. The normal operating range of the CS pin is 0.78 V to 0.195 V. There is additional protection if the CS pin reaches 1.5 V. This results in a UVLO reset and restart sequence.

The line input run and stop thresholds are determined by current information at the VS pin during the transistor on-time. While the VS pin is clamped close to GND during the transistor on-time, the current through R_S1 is monitored to determine a sample of the bulk capacitor voltage. A wide separation of run and stop thresholds allows clean start-up and shut-down of the power supply with the line voltage. The run current threshold is
225 µA and the stop current threshold is 80 µA.

The internal over-temperature protection threshold is 165°C. If the junction temperature reaches this threshold the device initiates a UVLO reset cycle. If the temperature is still high at the end of the UVLO cycle, the protection cycle repeats.

Protection is included in the event of component failures on the VS pin. If complete loss of feedback information on the VS pin occurs, the controller stops switching and restarts.