Table 1. Design Parameters

8.2.2.1 Stand-by Power Estimate

Assuming no-load stand-by power is a critical design parameter, determine estimated no-load power based on target converter maximum switching frequency and output power rating.

The followingEquation 7 estimates the stand-by power of the converter.

Equation 7.

For a typical USB charger application, the bias power during no-load is approximately 2.5 mW. This is based on 25-V VDD and 100-µA bias current. The output preload resistor can be estimated by V_OCV and the difference in the converter stand-by power and the bias power. Equation 8 shows output preload resistance accounts for bias power estimated at 2.5 mW.

Equation 8.

Typical startup resistance values for R_STR range from 1 MΩ to 5MΩ to achieve 2 s startup time. The capacitor bulk voltage for the loss estimation is the highest voltage for the stand-by power measurement, typically 325 V_DC, see Equation 9.

Equation 9.

For the total stand-by power estimation add an estimated 2.5 mW for snubber loss to the converter stand-by power loss, see Equation 10 and Equation 11.

Equation 10.

Equation 11.

8.2.2.2 Input Bulk Capacitance and Minimum Bulk Voltage

Determine the minimum voltage on the input capacitance, C_B1 and C_B2 total, in order to determine the maximum Np to Ns turns ratio of the transformer. The input power of the converter based on target full-load efficiency, minimum input RMS voltage, and minimum AC input frequency are used to determine the input capacitance requirement.

Maximum input power is determined based on V_OCV, I_OCC, and the full-load efficiency target, see Equation 12.

Equation 12.

Equation 13 provides an accurate solution for input capacitance based on a target minimum bulk capacitor voltage. To target a given input capacitance value, iterate the minimum capacitor voltage to achieve the target capacitance.

Equation 13.

8.2.2.3 Transformer Turns Ratio, Inductance, Primary-Peak Current

The maximum primary-to-secondary turns ratio can be determined by the target maximum switching frequency at full load, the minimum input capacitor bulk voltage, and the estimated DCM quasi-resonant time.

Initially determine the maximum available total duty cycle of the on time and secondary conduction time based on target switching frequency and DCM resonant time. For DCM resonant time, assume 500 kHz if you do not have an estimate from previous designs. For the transition mode operation limit, the period required from the end of secondary current conduction to the first valley of the V_CE voltage is 1/2 of the DCM resonant period, or 1 µs assuming 500-kHz resonant frequency. D_MAX can be determined using Equation 14.

Equation 14.

Once D_MAX is known, the maximum turns ratio of the primary to secondary can be determined with the equation below. D_MAGCC is defined as the secondary diode conduction duty cycle during constant-current, CC, operation. It is set internally by the UCC28722 at 0.425. The total voltage on the secondary winding needs to be determined; which is the sum of V_OCV, the secondary rectifier V_F, and the cable compensation voltage (V_OCBC). For the 5-V USB charger applications, a turns ratio range of 13 to 15 is typically used, see Equation 15.

Equation 15.

Once an optimum turns ratio is determined from a detailed transformer design, use this ratio for the following parameters.

The UCC28722 constant-current regulation is achieved by maintaining a maximum D_MAG duty cycle of 0.425 at the maximum primary current setting. The transformer turns ratio and constant-current regulating voltage determine the current sense resistor for a target constant current.

Since not all of the energy stored in the transformer is transferred to the secondary, a transformer efficiency term is included in Equation 16. This efficiency number includes the core and winding losses, leakage inductance ratio, and bias power ratio to rated output power. For a 5-V, 1-A charger example, bias power of 1.5% is a good estimate. An overall transformer efficiency of 0.9 is a good estimate to include 3.5% leakage inductance, 5% core and winding loss, and 1.5% bias power.

Equation 16.

The primary transformer inductance can be calculated using the standard energy storage equation for flyback transformers. Primary current, maximum switching frequency and output and transformer power losses are included in Equation 17 and Equation 18. Initially determine transformer primary current.

Primary current is simply the maximum current sense threshold divided by the current sense resistance.

Equation 17.

Equation 18.

The secondary winding to auxiliary winding transformer turns ratio (N_AS) is determined by the lowest target operating output voltage in constant-current regulation and the VDD UVLO of the UCC28722. There is additional energy supplied to VDD from the transformer leakage inductance energy which allows a lower turns ratio to be used in many designs Equation 19

Equation 19.

8.2.2.4 Transformer Parameter Verification

The transformer turns ratio selected affects the transistor V_C and secondary rectifier reverse voltage so these should be reviewed. The UCC28722 does require a minimum on time of the transistor (t_ON) and minimum D_MAG time (t_DMAG) of the secondary rectifier in the high line, minimum load condition. The selection of f_MAX, L_P and R_CS affects the minimum t_ON and t_DMAG.

The secondary rectifier and transistor voltage stress can be determined by Equation 20.

Equation 20.

For the transistor V_C voltage stress, Equation 21, an estimated leakage inductance voltage spike (V_LK) needs to be included.

Equation 21.

Equation 22 and Equation 23 are used to determine if the minimum t_ON target of 300 ns and minimum t_DMAG target of 1.2 µs is achieved.

Equation 22.

Equation 23.

8.2.2.5 Output Capacitance

The output capacitance value is typically determined by the transient response requirement from no-load. For example, in some USB charger applications there is a requirement to maintain a minimum V_O of 4.1 V with a load-step transient of 0 mA to 500 mA . Equation 24 assumes that the switching frequency can be at the UCC28722 minimum of f_SW(min).

Equation 24.

Another consideration of the output capacitor is the ripple voltage requirement which is reviewed based on secondary peak current and ESR. A margin of 20% is added to the capacitor ESR requirement in Equation 25.

Equation 25.

8.2.2.6 VDD Capacitance, C_DD

The capacitance on VDD needs to supply the device operating current until the output of the converter reaches the target minimum operating voltage in constant-current regulation. At this time, the auxiliary winding can sustain the voltage to the UCC28722. The total output current available to the load and to charge the output capacitors is the constant-current regulation target, I_OCC. Equation 26 assumes all the output current of the flyback is available to charge the output capacitance from 0 V to V_OCC. If the converter is going to be loaded during the time the output is ramping from 0 V to V_OCC, that load current must be subtracted for the available output current limit value, I_OCC. There is 1 V of margin added to VDD in the calculation.

Equation 26.

8.2.2.7 VS Resistor Divider, Line Compensation, and Cable Compensation

The VS divider resistors determine the output voltage regulation point of the flyback converter, also the high-side divider resistor (R_S1) determines the line voltage at which the controller enables continuous DRV operation. R_S1 is initially determined based on transformer auxiliary to primary turns ratio and desired input voltage operating threshold in Equation 27.

Equation 27.

The low-side VS pin resistor is selected based on desired V_O regulation voltage in Equation 28.

Equation 28.

The UCC28722 can maintain tight constant-current regulation over input line by utilizing the line compensation feature. The line compensation resistor (R_LC) value is determined by current flowing in R_S1 and expected base drive and transistor turnoff delay in Equation 29. Assume a 50-ns internal delay in the UCC28722.

Equation 29.

The UCC28722 has adjustable cable drop compensation. The resistance for the desired compensation level at the output terminals can be determined using Equation 30.

Equation 30.

8.2.2.8 Startup Resistance and Startup Time

When the VDD capacitor is known, there is a tradeoff to be made between startup time and overall standby input power to the converter. Faster startup time requires a smaller startup resistance, which results in higher standby input power in Equation 31.

Equation 31.