10.1 Layout Guidelines

In order to increase the reliability and feasibility of the project it is recommended to adhere to the following guidelines for PCB layout.

1. Minimize stray capacitance on the VS node. Place the voltage sense resistors (R_S1 and R_S2 in Figure 24 through Figure 27) close to the VS pin.
2. TI recommends to connect the HV input to a non-switching source of high voltage, not to the MOSFET drain, to avoid injecting high-frequency capacitive current pulses into the device.
3. Arrange the components to minimize the loop areas of the switching currents as much as possible. These areas include such loops as the transformer primary winding current loop, the MOSFET gate-drive loop, the primary snubber loop, the auxiliary winding loop and the secondary output current loop.

10.2 Layout Example

The partial layout example of Figure 28 demonstrates an effective component and track arrangement for low-noise operation on a single-layer printed circuit board. Actual board layout must conform to the constraints on a specific design, so many variations are possible.

Figure 28. UCC28730-Q1 Partial Layout Example