ZHCSBB1D July 2013 – March 2018 UCC28740
PRODUCTION DATA.
- 1 特性
- 2 应用
- 3 说明
- 4 修订历史记录
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 Custom Design With WEBENCH® Tools
- 8.2.2.2 Standby Power Estimate and No-Load Switching Frequency
- 8.2.2.3 Input Bulk Capacitance and Minimum Bulk Voltage
- 8.2.2.4 Transformer Turns-Ratio, Inductance, Primary Peak Current
- 8.2.2.5 Transformer Parameter Verification
- 8.2.2.6 VS Resistor Divider, Line Compensation
- 8.2.2.7 Output Capacitance
- 8.2.2.8 VDD Capacitance, CVDD
- 8.2.2.9 Feedback Network Biasing
- 8.2.3 Application Curves
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文档支持
- 12机械、封装和可订购信息
8.2.2.5 Transformer Parameter Verification
Because the selected transformer turns-ratio affects the MOSFET VDS and the secondary and auxiliary rectifier reverse voltages, a review of these voltages is important. In addition, internal timing constraints of the UCC28740 require a minimum on time of the MOSFET (tON) and a minimum demagnetization time (tDM) of the transformer in the high-line minimum-load condition. The selection of fMAX, LP, and RCS affects the minimum tON and tDM.
Equation 18 and Equation 19 determine the reverse voltage stresses on the secondary and auxiliary rectifiers. Stray inductance can impress additional voltage spikes upon these stresses and snubbers may be necessary.
For the MOSFET VDS peak voltage stress, an estimated leakage inductance voltage spike (VLK) is included.
Equation 21 determines if tON(min) exceeds the minimum tON target of 280 ns (maximum tCSLEB). Equation 22 verifies that tDM(min) exceeds the minimum tDM target of 1.2 µs.
