7.3.2 Secondary-Side Optically Coupled Constant-Voltage (CV) Regulation

Figure 9 shows a simplified flyback convertor with the main output-regulation blocks of the device shown, along with typical implementation of secondary-side-derived regulation. The power-train operation is the same as any DCM-flyback circuit. A feedback current is optically coupled to the controller from a shunt-regulator sensing the output voltage.

Figure 9. Simplified Flyback Converter
(with the Main Voltage Regulation Blocks)

In this configuration, a secondary-side shunt-regulator, such as the TL431 (or ATL431), generates a current through the input photo-diode of an optocoupler. The photo-transistor delivers a proportional current that is dependent on the current-transfer ratio (CTR) of the optocoupler to the FB input of the UCC28742 controller. This FB current then converts into the V_CL by the input-mirror network, detailed in the device block diagram (see Functional Block Diagram). Output-voltage variations convert to FB-current variations. The FB-current variations modify the V_CL which dictates the appropriate I_PP and f_SW necessary to maintain CV regulation. At the same time, the VS input senses the auxiliary winding voltage during the transfer of transformer energy to the secondary output to monitor for an output overvoltage condition. When f_SW reaches the converter target maximum frequency (i.e., corresponding de-mag time duty reaches 0.475), Constant Current Limit is triggered and further increases in V_CL cannot increase f_SW anymore. (see Figure 10, Control Law and Constant Current Limit and Delayed Shutdown)

Figure 10. Auxiliary Winding Voltage

The UCC28742 samples the VS input voltage at the end of demagnetization time for output overvoltage detection and to determine the total demagnetization time for output current control in Constant Current Limit operation.

In order to maintain best performance of these functions the reset time and ringing of the auxiliary winding voltage should meet certain guidelines. Referring to Figure 11, the width of the leakage spike at the VS input should be less than t_{DM_BLANK}. Minimum t_{DM_BLANK} is 3 µs at maximum peak priamry current levels and proportionally less at lower peak primary current levels (the lowest 0.75 µs should be observed at high line and no load condition). In addition, any ringing following the spike should be reduced to < 160 mVpp (scaled to the VS pin) 200 ns before the end of the demagnetization time.

As mentioned in Device Functional Modes, when I_PP < I_PP(max), the device operation enters a “Wait” state during each switching cycle of its non-switching portion as shown in Figure 11. In the Wait state, the device bias current changes to I_WAIT (typical 80 µA) from I_RUN (typical 1.8 mA), reducing its bias power to help boost efficiency at light load and to reduce no-load input power.

Figure 11. Auxiliary Waveform Details