7.3.4 Constant Current Limit and Delayed Shutdown

Timing information at the VS pin and current information at the CS pin allow accurate regulation of the secondary constant current limit, CCL, thus to achieve load over-current protection. The control law dictates that as power is increased in CV regulation and approaching CCL the primary-peak current is at I_PP(max). Referring to Figure 13 below, the primary peak current (I_PP), turns-ratio (N_S/N_P), secondary demagnetization time (t_DMAG), and switching period (t_SW) determine the secondary average output current. Ignoring leakage inductance effects, the average output current is given by Equation 5. By regulating the secondary rectifier conduction duty cycle, the output current limit is achieved for given I_PP and transformer turns-ratio. When the load increases, the secondary-side rectifier conduction duty cycle keep increasing. Once this duty cycle reaches preset value of 0.475, the converter switching frequency stops increasing and starts adjusting to reduce and maintain 0.475 secondary-side duty cycle. Therefore, the output constant current limit is achieved. Because the current is kept constant, the increasing load results in lower output voltage.

Equation 5.

Figure 13. Transformer Currents

As shown in Figure 14 below, CV mode operation is from I_O = 0 to < I_OCC; at I_O = I_OCC, the operation enters constant current limit mode and V_O starts to drop as the load resistance becomes further lower while I_O is maintained at I_OCC for a time interval specified by t_{OVL_TIME} typically 120 ms then DRV stops to achieve converter output delayed shutdown. During the 120-ms timing interval, if load I_O reduces to < I_OCC, the timer will be reset and no shutdown will occur. The V-I curve corresponding to the operation is shown in Figure 14, and the delayed shutdown timing diagram is shown in Figure 15. Note (1) The timer t_{OVL_TIME} is triggered whenever I_O reaches I_OCC and reset when I_O drops to < I_OCC before 120ms-time-out. (2) during 120-ms time interval, when load resistance becomes so low during constant current interval that causes the device VDD to reach its V_VDD(off) and then the shutdown will be through VDD undervoltage lockout instead of through Constant Current Limit and Delayed Shutdown. In such a case, the shutdown can happen before 120ms timer out.

Figure 14. Typical Target Output V-I Characteristics

Figure 15. Output Delayed Shutdown Timing