ZHCSHY7A April 2018 – May 2018 UCC28742
PRODUCTION DATA.
The following table illustrates a typical subset of high-level design requirements for a particular converter of which many of the parameter values are used in the various design equations in this section. Other necessary design parameters, VBULK(min) for example, may not be listed in such a table. These values may be selected based on design experience or other considerations, and may be iterated to obtain optimal results.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
INPUT CHARACTERISTICS | ||||||
VIN | AC-line input voltage | 85 | 115/230 | 265 | VRMS | |
fLINE | Line frequency | 47 | 50/60 | 63 | Hz | |
PSTBY | No-load input power | VIN = typ, IO = 0A | 65 | mW | ||
OUTPUT CHARACTERISTICS | ||||||
VO | DC output voltage | VIN = typ, IO = 0 to IOR | 5 | V | ||
VRIPPLE | Output voltage ripple | VIN = typ, IO = IOR | 50 | mV | ||
IOR | Output rated current | VIN = min to max | 2.0 | A | ||
IOVL | Overload current Limit | VIN = typ | 2.05 | A | ||
OVL delay | Overload shutdown delay | VIN= typ, IO = IOCC | 120 | ms | ||
ηAVG | Average efficiency | VIN= typ, average of 25%, 50%, 75%, and 100% Load | 82 | % | ||
SYSTEMS CHARACTERISTICS | ||||||
fsw | Switching frequency | 0.2 | 65 | kHz |