7.3.1 BUR Pin (Programmable Burst Mode)

The voltage at the BUR pin (V_BUR) sets a target peak current threshold (V_CST(BUR)) which programs the onset of adaptive burst mode (ABM) and determines the clamped peak current level of switching cycles in each burst packet. When V_BUR is designed higher, ABM will start at heavier output load conditions with higher peak current, so the benefit is the higher light-load efficiency but the side effect is a larger burst output voltage ripple. Therefore, 50% to 60% of output load at high line is the recommended highest load condition entering into ABM (I_o(BUR)) for both Si and GaN-based ACF designs. The gain between V_BUR and V_CST(BUR) is a constant gain of K_BUR-CST, so setting V_CST(BUR) just requires properly selecting the resistor divider on the BUR pin formed by R_BUR1 and R_BUR2. V_BUR should be set between 0.7 V and 2.4 V. If V_BUR is less than 0.7 V, V_CST(BUR) holds at 0.7 V / K_BUR-CST. If V_BUR is higher than 2.4 V, V_CST(BUR) stays at 2.4 V / K_BUR-CST.

Equation 1.

In order to enhance the mode transition between ABM and Low Power Mode (LPM), a programmable offset voltage (ΔV_BUR) is generated on top of the V_BUR setting in ABM through an internal 2.7-μA current source (I_BUR), as shown in Figure 12. In ABM mode, V_BUR is set through the resistor voltage divider to fulfill the target average efficiency. After transition from ABM to LPM, the current source is enabled in LPM and flows out of the BUR pin, so ΔV_BUR can be programmed based on the Thevenin resistance on the BUR pin, which can be expressed as

Equation 2.

Figure 12. Hysteresis Voltage Generation on BUR Pin

When V_BUR becomes higher after transition to LPM, the initial peak magnetizing current in LPM is increased with larger energy per switching cycle in a burst packet, which forces UCC28780 to stay in LPM with a higher feedback current than ABM. If ΔV_BUR is designed too small, it is possible that mode toggling between LPM and ABM can occur resulting in audible noise. For that situation, ΔV_BUR greater than 100 mV is recommended. To minimize the noise coupling effect on V_BUR, a filter capacitor on the BUR pin (C_BUR) may be needed. C_BUR needs to be properly designed to minimize the delay of generating ΔV_BUR in time during mode transition. It is recommended that C_BUR should be sized small enough to ensure ΔV_BUR settles within 40 μs, corresponding to the burst frequency of 25 kHz in LPM (f_LPM). Based on three RC time constants representing 95% of a settled steady state value from a step response, the design guide of C_BUR is expressed as

Equation 3.