7.3.5 HVG and SWS Pins

The HVG pin provides a controlled voltage to the gate of the depletion-mode MOSFET (Q_S), enabling Q_S to serve both V_VDD startup and lossless ZVS sensing from the high-voltage switch node (V_SW). During V_VDD startup, the UVLO circuit commands two power-path switches connecting SWS and HVG pins to VDD pin with two internal current-limit resistors (R_DDS and R_DDH) separately, as shown in Figure 16. In this configuration, Q_S behaves as a current source to charge the VDD capacitor (C_VDD). R_DDS is set at 12 kΩ when V_VDD is below 1 V to limit the maximum fault current under VDD pin short events. R_DDS is reduced to 1 kΩ when V_VDD rises above 1 V to allow V_VDD to charge faster. The maximum charge current (I_SWS) is affected by R_DDS, the external series resistance (R_SWS) from SWS pin to Q_S, and the threshold voltage of Q_S (V_TH(Qs)). I_SWS can be calculated as

Equation 7.

Figure 16. Operation of the VDD Startup Circuit

After V_VDD reaches V_VDD(ON), the two power-path switches open the connections among SWS, HVG, and VDD pins. At this point, a third power-path switch connects an internal 11-V regulator to the HVG pin for configuring Q_S to perform lossless ZVS sensing. As Q_S gate is fixed at 11 V and the drain pin voltage of Q_S becomes higher than the sum of Q_S threshold voltage (V_TH(Qs)) and the 11-V gate voltage, Q_S turns off and the source pin voltage of Q_S can no longer follow the drain pin voltage change, so this gate control method makes Q_S act as a high-voltage blocking device with the drain pin connected to V_SW. When the controller is switching, V_SW can be lower than 11 V, so Q_S turns on and forces the source pin voltage to follow V_SW, becoming a replica of the V_SW waveform at the lower voltage level, as illustrated in Figure 17.

The limited window for monitoring the V_SW waveform suffices for ZVS control of the UCC28780, since the ZVS tuning threshold (V_TH(SWS)) is lower than that, which is at 9 V for V_SET = 5 V and at 4 V for V_SET = 0 V. The 9-V threshold is the auto-tuning target of the internal adaptive ZVS control loop for realizing a partial ZVS condition on the ACF using Si primary switches. On the other hand, performing full ZVS operation is more suitable for the ACF with GaN primary switches. The 4-V threshold can help to better compensate sensing delay between V_SW and the SWS pin more than using a 0-V threshold. The internal 11-V regulator requires a high quality ceramic bypass capacitor (C_HVG) between the HVG pin and GND for noise filtering and providing compensation to the regulator circuitry. The minimum C_HVG value is 2.2 nF and an X7R-type dielectric capacitor is recommended. The controller enters a fault state if the HVG pin is open or shorted to GND during V_VDD start-up, or if V_HVG overshoot is higher than V_HVG(OV) of 13.8 V in run state. The output short current of HVG regulator (I_S(HVG)) is self-limited to around 1mA.

Figure 17. ZVS Sensing by Reusing the VDD Startup Circuit