7.4.2 Dead-Time Optimization

The dead-time optimizer in Figure 19 controls the two dead-times: the dead-time between PWMH falling edge and PWML rising edge (t_Z), as well as the dead-time between PWML falling edge and PWMH rising edge (t_D(PWML-H)).

The adaptive control law for t_Z of UCC28780 utilizes the line feed-forward signal to extend t_Z as V_BULK reduces, as shown in Figure 21. The VS pin senses V_BULK through the auxiliary winding voltage (V_AUX) when the low-side switch (Q_L) is on. The auxiliary winding creates a line-sensing current (I_VSL) out of the VS pin flowing through the upper resistor of the voltage divider on VS pin (R_VS1). Minimum t_Z (t_Z(MIN)) is set at V_BULK(MAX) through the RTZ pin. When I_VSL is lower than 666 μA, t_Z linearly increases and the maximum t_Z extension is 140% of t_Z(MIN).

Figure 21. t_Z Control Optimized for Wide Input Voltage Range

The control law for t_D(PWML-H) of UCC28780 is programmable based on the SET pin voltage. When V_SET = 0 V, a fixed delay around 40 ns is used to fit a GaN-based ACF with a fast dV/dt on the V_SW rising edge. With V_SET = 5 V, the dead-time optimization is enabled to intelligently adapt to the effect of nonlinear junction capacitance of Si MOSFETs on the dV/dt of V_SW rising edge. The high capacitance region of the C_OSS curve for the Si Q_L creates a shallow ramping on V_SW after PWML turns off. When C_OSS of Si Q_L moves to the low capacitance region with V_SW increasing, V_SW starts to ramp up very quickly. Since the changing slope varies with different peak magnetizing currents as output load changes, using a fixed dead-time can potentially cause hard-switching on the high-side clamp switch (Q_H) if the dead-time is not long enough. UCC28780 utilizes the zero crossing detect (ZCD) signal on the auxiliary-winding voltage to identify if V_SW overcomes the shallow ramping, and generates a 50-ns delay (t_D(VS-PWMH)) before turning on PWMH. This feature allows cycle-by-cycle dead-time adjustment to avoid hard-switching of Q_H, while providing fast turn-on timing for Q_H to minimize the body-diode conduction time.

Figure 22. t_D(PWML-H) Control Optimized for GaN and Si FETs