7.4.5 Adaptive Burst Mode (ABM)

As the load current reduces to I_O(BUR) where V_CS reaches to V_CST(BUR) threshold, ABM starts and V_CS is clamped. The peak magnetizing current and the switching frequency (f_SW) of each switching cycle are fixed for a given input voltage level. V_CST(BUR) is programmed by the BUR pin voltage (V_BUR). The PWM pattern of ABM is shown in Figure 25. When RUN goes high, a delay time between RUN and PWML (t_D(RUN-PWML)) is given to allow both the gate driver and the UCC28780 time to wake up from a wait state to a run state. PWML is set as the first pulse to build up the bootstrap voltage of the high-side driver before PWMH starts switching. The first PWML pulse turns on Q_L close to a valley point of the DCM ringing on the switch-node voltage (V_SW) by sensing the condition of zero crossing detection (ZCD) on the auxiliary winding voltage (V_AUX). The following switching cycles operate in a ZVS condition, since PWMH is enabled. As the number of PWML pulses (N_SW) in the burst packet reaches its target value, the RUN pin pulls low after the ZCD of the last switching cycle is detected, and forces the half-bridge driver and UCC28780 into a wait state for the quiescent current reduction of both devices. In this mode, the minimum off-time of the RUN signal is 2.2 µs and the minimum on-time of PWML is limited to the leading-edge blanking time (t_CSLEB) of the peak current loop. However, more grouped pulses means more risk of higher output ripple and higher audible noise. The following equation estimates how burst frequency (f_BUR) varies with output load and other parameters.

Equation 11.

As I_O< I_O(BUR), f_BUR can become lower than the audible noise range if N_SW is fixed. In ABM, N_SW is modulated to ensure f_BUR stays above 20 kHz by monitoring f_BUR in each burst period. As I_O reduces, f_BUR becomes lower and reaches a predetermined low-level frequency threshold (f_BUR(LR)) of 25 kHz. The ABM loop commands N_sw of both PWML and PWMH to be reduced by one pulse to maintain f_BUR above f_BUR(LR). At the same time, the burst frequency ripple on the output voltage reduces as N_SW drops with the load reduction. As I_O increases, f_BUR becomes higher and reaches a predetermined high-level frequency threshold (f_BUR(UP)) of 34 kHz. The ABM loop commands N_SW to be increased by one pulse to push f_BUR back below f_BUR(UP).

This algorithm maximizes the number of pulses in each burst packet to improve light-load efficiency, while also limiting the burst output ripple and audible noise. As I_O moves below the boundary between AAM and ABM, the maximum N_SW is nine and the minimum N_SW is two. As I_O is close to the boundary between AAM and ABM, the maximum N_SW can be higher than nine, to provide a smoother mode transition. When the load slightly increases in this boundary, more than nine pulses are generated in a burst packet as Figure 26 shows. f_BUR starts to move lower than 20kHz. The burst pattern with disordered N_SW and inconsistent f_BUR among the asymmetric burst packets generates a frequency spreading effect to weaken the strength of potential audible noise, when the controller operates in the transition region. It is found that dip varnishing the transformer is a very effective way to mitigate the minor audible noise around the mode transition. ABM operation with lower peak magnetizing current through lower BUR-pin voltage can also help to minimize the potential audible noise. Generally speaking, entering ABM at around 50 to 60% of output load and using a varnished transformer provides good balance between the light-load efficiency and smooth mode transitions with minimal audible noise.

Figure 25. PWM Pattern in ABM

Figure 26. Mode Transition Behavior between AAM and ABM