7.4.10.2 Output Over-Voltage Protection

VS pin senses the positive voltage level of the auxiliary winding voltage (V_AUX) to detect an over-voltage condition of V_O. When an OVP event is triggered, UCC28780 stops switching and there is a 1.5-s fault recovery time (t_FDR) before any V_O restart attempt is made. As Q_L turns off, the settled V_AUX is equal to (V_O+V_F) x N_AS, where N_AS is the auxiliary-to-secondary turns ratio of the transformer, N_A / N_S, and V_F is the forward voltage drop of the secondary-side rectifier. The VS pin senses V_AUX through a voltage divider formed by R_VS1 and R_VS2. The pin voltage (V_VS) is compared with an internal OVP threshold (V_OVP). If V_VS ≥ V_OVP condition is qualified for three consecutive PWML pulses, the controller stops switching, brings RUN pin low, and initiates the 1.5-s time delay. During this long delay time, only the UVLO-cycle of V_VDD is active, and there are no test pulses of PWML. After the 1.5-s timeout is completed and V_VDD reaches the next V_VDD(OFF), a normal start sequence begins. The calculation of R_VS2 is

Equation 15.

The long t_FDR timer helps to protect the power stage components from the large current stress during every restart. After OVP is triggered, V_O may be brought down quickly by the output load current. If OVP were reset directly after one UVLO cycle of VDD without the 1.5-s delay, the first PWMH pulse turns on Q_H under the condition of a large voltage difference between the high clamp capacitor voltage (V_CLAMP) and the low reflected voltage. A large current can flow through the clamp switch (Q_H) and secondary rectifier. Therefore, the 1.5-s timer of UCC28780 allows V_CLAMP to drop to a lower voltage level through a bleeding resistor (R_BLEED) in parallel with C_CLAMP before the next V_O restart attempt, such that the current stress can be minimized. A large R_BLEED can be used with the long time-out to minimize the impact on standby power. For example, to discharge V_CLAMP to 10% of its normal level in 1.5 s, only 3 mW of additional standby power is added with R_BLEED = 2.8 MΩ and C_CLAMP = 220 nF. Figure 32 illustrates the timing sequence as V_CLAMP is discharged to a residual voltage (V_RESIDUAL) in 1.5 s. R_BLEED also helps to reduce the voltage overcharge on the clamp capacitor in LPM and SBP modes in which PWMH is disabled, so the voltage stress in the passive-clamp operation can be controlled.

During LPM to ABM mode transition, it is possible to falsely trigger OVP if the setting does not have enough design margin. In LPM mode with a disabled PWMH, the leakage energy of the transformer charges V_CLAMP higher than the reflected voltage. When the controller enters into ABM and the PWMH is enabled, the active-clamp circuit of ACF needs to take some time to balance the voltage difference, depending on the clamp capacitor value. As a result, V_AUX can sense the higher V_CLAMP condition during the voltage balancing and the controller may treat this as an OVP event, even though V_O still stays in regulation and does not reach the actual OVP point. It may only happen with a large C_CLAMP design, so slightly increasing the OVP setting can resolve the problem.

Figure 32. Timing Diagram of C_CLAMP Discharging During 1.5-s Recovery Time