7.4.10.4 Programmable Over-Power Protection

The over-power protection (OPP) enables the ACF to operate in an over-power condition for a limited amount of time, so the UCC28780 can support a power stage design with peak power requirements. As shown in Figure 34, when V_CST is higher than the threshold voltage of the OPP curve (V_CST(OPP)), a 160-ms timer starts. If V_CST remains higher than V_CST(OPP) continuously for 160 ms, the long 1.5-s timer starts and the controller stays in fault state without switching. This long recovery time reduces the average current during a sustained over-power event. The system benefits includes the reduction of thermal stress in high density adapters and the protection of its output cable.

The OPP function uses I_VSL as a line feed-forward signal to vary V_CST(OPP) depending on V_BULK, in order to make the OPP trigger point constant over a wide line voltage range. The UCC28780 allows programing of the OPP curve by adding a line-compensation offset voltage on the CS pin through a resistor (R_OPP) connected between the CS pin and current-sense resistor (R_CS). An internal current source flowing out of CS pin creates the offset voltage on R_OPP. This current level is equal to I_VSL divided by a constant gain of K_LC. As R_OPP increases, the OPP trigger point becomes lower at high line, so lower peak magnetizing current is allowed to run continuously.

The highest threshold of OPP curve (V_CST(OPP1)) of 0.6 V helps to determine R_CS value at V_BULK(MIN).

Equation 16.

where P_O(OPP) is the output power that triggers OPP, and t_D(CST) is the sum of all delays in the peak current loop which contributes additional peak current overshoot. t_D(CST) consists of propagation delay of the low-side driver, current sense filter delay (R_OPP x C_CS), internal CS comparator delay (t_D(CS)), and nonlinear capacitance delay of Q_L. After R_CS is determined, R_OPP can be adjusted to keep a similar OPP point at highest line. Note that setting the OPP trigger point too far away from the full power may introduce more challenge on the thermal design, since the converter runs continuously with more power as long as the corresponding peak current is slightly less than OPP threshold.

Figure 34. CS-Pin Related Faults

Figure 35. Timing Diagram of OPP