7.4.11.2 Protections on HVG pin Fault

As shown in Figure 30, after V_VDD reaches V_VDD(ON), an internal 11-V regulator on the HVG pin should force V_HVG back to the regulation level before PWML starts switching. If the recommended HVG-pin capacitor (C_HVG) of 2.2 nF and the connection to the depletion-mode MOSFET (Q_S) are in place, the settling time of V_HVG to 11 V is much longer than 10 μs with a limited sink current of the regulator (I_SE(HVG)) to discharge C_HVG.

The first fault scenario is that if C_HVG is too small, or the HVG pin is open, the pin is not able to control Q_S correctly for the high-voltage sensing function of ZVS control, so no switching action will be performed. When either two situations happen, V_HVG settles to 11 V very quickly instead. Therefore, after a 10-μs delay from the instance of V_VDD reaching V_VDD(ON), UCC28780 checks if V_HVG is below 12 V for the pin-fault detection, and then performs one UVLO cycle of VDD directly without switching as the protection response. The above protection is to prevent the controller from generating PWM signals. However, when the HVG pin is open and disconnected from the Q_S gate, the source voltage of Q_S keeps increasing until the TVS on the SWS pin (D_SWS) starts to clamp the voltage continuously. To shrink the size of D_SWS without incurring too much thermal stress in the small package in this fault condition, it is highly recommended that a small Zener diode (D_HVG) between Q_S gate to ground should be used to limit the Q_S source voltage. Same as D_SWS, D_HVG should be higher than V_VDD(ON), so as to prevent interference with normal VDD startup.

The second fault scenario is the over-voltage condition of HVG pin after the converter starts switching. When the switch-node voltage (V_SW) rises with a high dV/dt condition, there is a charge current flowing through the junction capacitance of Q_S, and part of the current can charge up C_HVG. If the overshoot is too large, the voltage on the SWS pin also increases due to the nature of the depletion-mode MOSFET operation. UCC28780 detects the overshoot event on HVG pin with an over-voltage threshold (V_HVG(OV)) of 13.8V cycle-by-cycle. When V_HVG is higher than V_HVG(OV) for three consecutive PWML pulses, the HVG over-voltage protection is triggered which performs one UVLO cycle of VDD.

The third fault scenario is an HVG pin short event at the beginning of VDD startup, and Q_S is not able to charge up the VDD capacitor to V_DD(ON), so there is no chance to enable the controller.