The VDD pin is the primary bias for the internal 5-V REF regulator, internal 13-V P13 regulator, other internal references, and the undervoltage lock-out (UVLO) circuit. As shown in Figure 7-5, the UVLO circuit connected to the VDD pin controls the internal power-path switches among VDD, P13, and SWS pins, in order to allow an external depletion-mode MOSFET (Q_S) to be able to perform both V_VDD startup and switch-node voltage (V_SW) sensing for ZVS control after startup. During startup, SWS and P13 pins are connected to VDD pin allowing Q_S to charge the VDD capacitor (C_VDD) from the V_SW.

After the VDD startup completes, the ZVS discriminator block and switching logic are enabled. Then, the transformer starts delivering energy to the output capacitor (C_O) every switching cycle, so both output voltage (V_O) and auxiliary winding voltage (V_AUX) increase.

As V_AUX is high enough, the auxiliary winding takes over to power V_VDD. The UVLO circuit provides a turn-on threshold of V_VDD(ON) at 17 V and turn-off threshold of V_VDD(OFF) at 10.6 V. For fixed output voltage designs, the wide V_VDD range can accommodate lower values of VDD capacitor (C_VDD) and support shorter power-on delays.

For a fixed output voltage design, the rectified V_AUX is directly connected to the VDD pin. As V_VDD reaches V_VDD(ON), the SWS pin is disconnected from the VDD pin by the internal power path switch, so the C_VDD size has to be sufficient to hold V_VDD higher than V_VDD(OFF) until the positive auxiliary winding voltage is high enough to take over bias power delivery during V_O soft start. Therefore, the calculation of minimum capacitance (C_VDD(MIN)) needs to consider the discharging effect from the sink current of the UCC28781-Q1 during switching in its run state (I_RUN(SW)), the average operating current of driver (I_DR), and the average gate charge current of half-bridge FETs (I_Qg) throughout the longest duration of V_O soft-start (t_SS(MAX)) sequence.

t_SS(MAX) estimation should consider the averaged soft-start current (I_SEC(SS)) on the secondary side of the converter, load current on the output (I_O(SS)) during start-up (if any), maximum output capacitance (C_O(MAX)), and a 0.7-ms time-out potentially being triggered in the startup sequence. Include 1 ms in the equation to be the worst-case condition of the 0.7-ms timer.

During the V_O soft-start sequence, V_CST reaches the maximum current threshold on the CS pin (V_CST(MAX)) , so I_SEC(SS) at the minimum voltage of the input bulk capacitor (V_BULK(MIN)) can be approximated as:

where

• R_CS is the current sense resistor
• N_PS is primary-to-secondary turns ratio
• V_F is the forward voltage drop of the secondary rectifier