The UCC28781-Q1 provides an input OVP function on the FLT pin. Figure 7-39 shows the application circuit for the input OVP sensing. A resistor divider senses the bulk capacitor voltage, and the IOVP fault is triggered when V_FLT > 4.5 V for longer than 750 µs. The 750 µs delay helps to desensitize the abrupt bulk voltage spike during the line surge condition, such that the output voltage will not drop accidentally. After the IOVP fault is asserted, the switching will be terminated immediately and V_VDD will restart. When V_VDD reaches V_VDD(ON) of the following VDD cycle, the controller will check V_FLT first before switching, to avoid the switching device from being exposed to a high-voltage stress condition. The fault will be cleared when V_FLT < 4.43 V.

If longer than 750 µs delay is required, a filter capacitor between the FLT pin and AGND pin can create additional programmable delay. If the filter capacitor is too large, it may trigger the OTP fault on the FLT pin, if the ramp up time for V_FLT to rise above V_NTCTH is longer than t_FLT(NTC) after the RUN pin is pulled high. The resistor divider design does not need to consider the offset voltage effect from the 50 µA current source out of the FLT pin, because the controller will disable the current source once V_FLT > 2.5 V.

The goal of the internal 5.5-V clamp device on the FLT pin is to protect the pin from exceeding the voltage limit when one of the IOVP upper sensing resistor fails short. The maximum clamp current is 150 µA, so the resistor divider design needs to consider this limitation.

Figure 7-39 Bulk Capacitor Voltage Sensing for Input OVP