Under certain conditions, the IPC pin provides a 50-µA current from an internal source (I_IPC(SBP2)) which is controlled by logic as shown in Figure 7-9. The voltage on the VS pin is sampled during the demagnetization time to obtain an indication of the reflected output voltage (NVO). When the VS-pin voltage is lower than the 2.4-V lower LV mode threshold (V_VSLV(LR)), the LOW_NVO logic signal is pulled high, and the current source is enabled during the run state of all normal control modes (SBP1, SBP2, LPM, ABM, and AAM).

When the sampled VS-pin voltage is higher than the 2.5-V upper LV mode threshold (V_VSLV(UP)), the LOW_NVO logic signal becomes low. In the LOW_NVO = 0 V case, the 50-µA current source is enabled in the run state of SBP2 mode only.

To minimize stand-by power, the 50-µA source is always disabled during the wait state of any control mode. Additionally, if V_VDD falls lower than the 13-V survival-mode threshold, the INT_STOP logic signal is pulled high and the current source is disabled during survival mode operation, irrespective of the V_VS level.

Figure 7-9 Control Circuit Diagram to the IPC-Pin Current Source

The multi-function IPC pin can be programmed to obtain one or more of the following benefits:

1. Reduction of input power for special light-load and stand-by conditions
2. Improvement of light-load efficiency at lower output voltages, such as 5 V and 9 V
3. Reduction of burst-mode output ripple at lower output voltages
4. Reduction of the over-power limit at lower output voltages
5. Power management of a PFC controller, together with the S13 pin

To implement the benefit No. 1, connect a resistor R_IPC from IPC pin to AGND pin. The 50-µA current source establishes a voltage (V_IPC) across R_IPC to program an increase in the CS-pin peak primary current threshold at very light loads. The transfer function between V_IPC and the CS threshold (V_{CST_IPC}) in SBP2 mode is illustrated in Figure 7-10.

Proper sizing of R_IPC to AGND can further reduce the burst frequency in SBP2 for so-called tiny-load power and for stand-by power.

When V_IPC is less than 0.9 V (or IPC is shorted to AGND), V_{CST_IPC} threshold stays at the minimum level of 0.15 V. When V_IPC is set between 0.9 V and 1.8 V, V_{CST_IPC} is clamped at 0.27 V. For V_IPC between 1.8 V and 3.8 V, there is a linear programmable V_{CST_IPC} range between 0.27 V and 0.4 V. When V_IPC is greater than 3.8 V, V_{CST_IPC} remains clamped to 0.4 V. Be aware that high settings of V_{CST_IPC} may, in some cases, introduce higher output ripple in deep light-load condition or provoke audible noise.

Figure 7-10 IPC Transfer Function to Program the SBP2 Peak Current Threshold

Because the enable status of the IPC current source contains the very useful output voltage information from the LOW_NVO logic state, the IPC pin can be used to further optimize power stage performance over a wide output voltage range. To gain benefits No.2, No. 3, and No. 4 of the IPC function, connect R_IPC between the IPC pin and the CS pin, so that the current source can create additional CS-pin offset voltage on R_OPP when V_VS < 2.4 V. With higher CS offset, the operating range of the V_CST signal will be higher than the actual power stage peak current. This forces the controller to operate in AAM mode for a wider actual output load range, and forces the burst-mode threshold down to a lower power level.

Figure 7-11 shows the side effect of the IPC-to-CS connection if the R_IPC setting is the same. Because the controller enables 50 µA in the run state of SBP2, the lower peak magnetizing current of the IPC-to-CS connection makes the SBP2 burst frequency higher and results in weakening the stand-by power improvement. Therefore, a higher R_IPC is needed to increase V_{CST_IPC} to compensate the peak current change.

Figure 7-11 Effect of the CS-pin Offset Voltage from the IPC Pin

For benefit No. 5, the IPC pin can also be used to disable a PFC controller (if used) at all load conditions for lower voltage outputs to further improve the light-load efficiency . As shown in Power Management Function for a GaN Power IC and PFC Controller, the diode D_IPC in series with R_IPC is placed between IPC and CS pins, and V_IPC established at IPC is used to drive a small-signal switch Q_IPC to disable the PFC controller such as UCC28056.

When V_IPC is higher than its threshold voltage, Q_IPC can pull low the COMP pin voltage of a PFC controller, so its switching is disabled. As a consequence, PFC output voltage drops from the typical 400-V regulation level to the peak value of the AC line. This lowers the bulk voltage, which reduces the ZVS energy, which increases power stage efficiency for low voltage outputs. Furthermore, the power loss of the PFC power stage is out of the efficiency equation. One design example for those components are C_S13(ZVSF) = 22 nF, C_S13(PFC) = 0.22 µF, C_IPC = 10 nF, R_IPC = 69.8 kΩ, R_IPC2 = 10 MΩ, and R_IPC3 = 20 kΩ. Choose Q_IPC with threshold voltage less than 1.5 V to ensure that V_IPC is sufficient to achieve low on-resistance (R_DS(on)) even at very low burst frequencies.