The UCC28781-Q1 is a transition-mode zero-voltage-switching flyback (ZVSF) controller equipped with advanced control schemes to enable significant size reduction of passive components for higher power density and higher average efficiency. Its control law is optimized for Silicon (Si) and Gallium Nitride (GaN) power FETs in a single-switch flyback configuration at high frequencies. In burst mode at very light loads the switching frequency may increase up to 1.5 MHz.

The ZVSF control of the UCC28781-Q1 is capable of auto-tuning the on-time of a secondary-side synchronous rectifier switch (Q_SR) by using a unique lossless ZVS-sensing network connected between the switch-node voltage (V_SW) and the SWS pin. The ZVSF controller is designed to adaptively achieve targeted full-ZVS or partial-ZVS conditions for the primary-side main switch (Q_L) with minimum circulating energy over wide operating conditions. Auto-tuning eliminates the risk of losing ZVS due to component tolerance, temperature, and input/output voltage variations, since the Q_SR on-time is corrected cycle-by-cycle.

Dead-times between PWML (controls Q_L) and PWMH (controls Q_SR) are optimally adjusted to help minimize the circulating energy required for ZVS as operating conditions change. Therefore, the overall system efficiency is improved and more consistent in mass production of the soft-switching topology. The programming features of the RTZ, RDM, BUR, IPC, and SET pins provide rich flexibility to optimize the power stage efficiency across a range of output power and operating frequency levels.

The UCC28781-Q1 uses five different steady-state operating modes to maximize efficiency over wide load and line ranges:

1. At higher load levels, adaptive amplitude modulation (AAM) adjusts the peak primary current.
2. In the medium-load range, adaptive burst mode (ABM) modulates the pulse count of each burst packet.
3. In the light-load range, low power mode (LPM) reduces the peak primary current of each two-pulse burst packet.
4. During very light-load conditions, stand-by power mode 1 (SBP1) minimizes the power loss.
5. During no-load conditions, stand-by power mode 2 (SBP2) minimizes the power loss.

During the system transient events such as the output load step down and output voltage overshoots, V_VDD may be reduced close to the 10.5-V UVLO-off threshold. In such cases, a sixth non-steady-state mode called survival mode (SM) is triggered to maintain V_VDD above 13 V and to reduce the size of the hold-up VDD capacitor.

The switching frequency-dither function is active in AAM to help reduce conducted-EMI noise and allow EMI filter size reduction. The 23-kHz dithering pattern and magnitude are designed to avoid audible noise, minimize efficiency influence, and desensitize the effect of the output voltage feedback loop response effect on the EMI attenuation. The dither function at low line can be programmed into disable mode based on the brown-in voltage setting, so the option provides design flexibility to balance the worst-case low-line efficiency and EMI. The dither fading feature smoothly disables the dither signal when the output load is close to the transition point between AAM and ABM. The 23-kHz dither frequency is high enough to allow a higher control-loop bandwidth for improved load transient response without distorting the dither signal and impairing EMI.

The unique burst mode control in ABM, LPM, and two SBP modes maximizes the light-load efficiency of the ZVSF power stage while avoiding the concerns of conventional burst operation - such as high output ripple and audible noise. The internal ramp compensation can stabilize the burst control loop without an external compensation network. The burst control provides an enable signal through the RUN pin to dynamically manage the static current of the SR gate-driver and also adaptively disables the drive signal of Q_SR. The internal drivers of RUN and PWMH can supply and disconnect the 5-V bias voltage to a digital isolator through a small-signal diode. The disconnect switch inside the S13 pin can directly control the 13-V bias voltage to a low-side GaN driver. These power management functions with RUN, PWMH, and S13 pins can be used to minimize the quiescent power consumed by those devices during burst off time, further improving the converter’s light-load efficiency and reducing its stand-by power.

The S13 and IPC pins of the UCC28781-Q1 can be adapted to manage an upstream PFC stage to maximize the light-load efficiency of higher power applications. The S13 pin can supply a 13-V bias voltage to the PFC controller whenever the ZVSF controller is in the run state. The pin disconnects the bias voltage during the wait states of the burst mode operation. When the burst frequency is reduced in very light load conditions, the bias voltage will decay below UVLO and shut down PFC controller, so the power loss from PFC can be eliminated.

The PWML output is a strong driver for a Si power MOSFET with high capacitive loading, a GaN-based gate injection transistor (GIT) with continuous on-state current, or a GaN power IC with logic input. The maximum voltage level of PWML is clamped at 13 V to balance the conduction loss reduction and gate charge loss of Si MOSFET. A dedicated driver ground return pin (PGND) minimizes the parasitic impedance and noise coupling of the PWML gate-drive loop to achieve faster switching speed and reduced turn-off loss of Q_L. The short 15-ns propagation delay and narrow 110-ns minimum on-time enable more accurate ZVS control and higher switching frequency operation.

During initial power up or VDD restart, the ZVSF stops switching, so UCC28781-Q1 starts up the VDD supply voltage with an external high-voltage depletion-mode MOSFET between the ZVSF switch node and the SWS pin. Fast startup is achieved with low stand-by power overhead, compared with using the conventional high-voltage startup resistance to VDD. Moreover, the P13 pin biases the gate of the depletion-mode FET to also allow this MOSFET to be used in lossless ZVS-sensing. This arrangement avoids additional sensing devices.

The enhanced switching control of UCC28781-Q1 mitigates excessive drain-to-source voltage stress on a synchronous rectifier (SR) caused by temporary continuous conduction mode (CCM), so the power loss of an SR snubber can be reduced for higher efficiency. Additional PWML timing controls can avoid premature Q_L turn-on before the magnetizing current reaches to zero through an improved zero-crossing detection (ZCD) scheme of the VS pin.

The UCC28781-Q1 also integrates more robust protection features tailored to maximize system reliability and safety. These features include active X-capacitor discharge, internal soft start, brown in/out, output over-voltage (OVP), input line over-voltage (IOVP), output over-power (OPP), system over-temperature (OTP), switch over-current (OCP), output short-circuit protection (SCP), and pin faults. All fault responses are auto-recovery, which means that the controller will attempt to restart after the shut-down time elapses.

The X-capacitor discharge function can actively discharge the residual voltage on X2 safety capacitors to a safe level after AC-line voltage removal is detected through the XCD pins of UCC28781-Q1 and its external sensing circuit. If the AC-line voltage recovers within 2 seconds after the line removal, the controller will reset the fault state immediately and will attempt to restart without waiting to fully discharge the bulk input capacitor or VDD capacitor. Grounding the two XCD pins disables this function and eliminates the sensing circuit. Unlike other conventional flyback controllers, UCC28781-Q1 provides the design flexibility of using the X-capacitor discharge function based on application power level as it is decoupled from VDD startup and brown-in/out detection functions. Since those two functions are implemented on the SWS and VS pins, respectively, UCC28781-Q1 maintains the two functions even when the XCD-related components are fully removed.