The RUN pin is a logic-level output signal which enables PWM switching when active high. When RUN is low, all PWML and PWMH switching is disabled and the controller enters a low-current wait state.

In addition to enabling switching, RUN is capable of sourcing considerable current to bias an external gate driver and perform a power management function on the primary side of a digital isolator. It generates a 5-V logic output when the driver should be active, and pulls down to less than 0.5 V when the driver should be disabled. During the off-time of any burst mode, the RUN pin serves as a power-management function to dynamically reduce the static bias current of the isolator/ driver, so light-load efficiency can be further improved and stand-by power can be minimized.

As RUN goes high, while its voltage is less than 3 V, a 44-mA peak pull-up current is supplied from the internal P13 regulator. With this current, the RUN driver can quickly charge the primary-side decoupling capacitor of a digital isolator above its UVLO(ON) threshold. A Schottky diode can block discharge of this capacitor when RUN goes low. When the RUN voltage goes above 3 V, P13 stops providing current and the pull-up is supplied from the REF regulator, so the peak driving capability will be limited in order to avoid triggering the over-current protection of the REF regulator. When RUN is low for a long burst off-time, the decoupling capacitor of the digital isolator will be gradually discharged below its UVLO(OFF) threshold, so the isolator power loss can be minimized.

There are three delays between RUN going high to the first PWML pulse going high in each burst packet. The first delay is a fixed 2.2-μs delay time, intended to provide an appropriate "wake-up" time for the controller and the gate driver to transition from a wait state to a run state. The second delay is gated by the 10-V power-good threshold of the S13 pin. PWML will not go high until S13 voltage exceeds 10 V. The third delay is another 2.2-μs timeout, t_ZC in the electrical table, intended to turn on the low-side switch of the first switching cycle per burst packet around the valley point of DCM ringing by waiting for the zero-crossing detection (ZCD) on the auxiliary winding voltage (V_AUX). If ZCD is detected (on the VS input) before the t_ZC timeout elapses, PWML is immediately driven. If no ZCD is detected, PWML is driven when t_ZC elapses. The first two delays can be concurrent; the third delay is sequential.

Therefore, the minimum total delay time is 2.2 μs typically if V_S13 > 10 V and ZCD is detected immediately after the 2.2-μs wake-up time. If V_S13 < 10 V, the total delay time with tolerance over temperature is listed as t_D(RUN-PWML) in the electrical table.

Figure 7-12 Power Management Circuit

Figure 7-13 Power Management Waveform