The dead-time optimizer in Figure 7-21 controls the two dead-times: the dead-time between PWMH falling edge and PWML rising edge (t_Z), as well as the dead-time between PWML falling edge and PWMH rising edge (t_D(PWML-H)).

The adaptive control law for t_Z utilizes the line feed-forward signal to extend t_Z as V_BULK reduces, as shown in Figure 7-23. The VS pin senses V_BULK through the auxiliary winding voltage (V_AUX) when the primary side switch (Q_L) is on. The auxiliary winding creates a line-sensing current (I_VSL) out of the VS pin flowing through the upper resistor of the voltage divider on VS pin (R_VS1). Minimum t_Z (t_Z(MIN)) is set at V_BULK(MAX) through the RTZ pin. When I_VSL is lower than 666 μA, t_Z linearly increases and the maximum t_Z extension is 140% of t_Z(MIN).

Figure 7-23 t_Z Control Optimized for Wide Input Voltage Range

The control law for t_D(PWML-H) is adaptive with the slope variation of the switching node voltage, regardless of the SET-pin voltage as shown in Figure 7-24.

Figure 7-24 t_D(PWML-H) Control Optimized for GaN and Si FETs