The switching pattern in AAM forces PWML and PWMH to alternate in a complementary fashion with dead-time in between, as shown in Figure 7-30. As the load current reduces, the negative magnetizing current (I_M-) stays the same, while the positive magnetizing current (I_M+) reduces by the internal peak current loop to regulate the output voltage. I_M+ generates a current-feedback signal (V_CS) on the CS pin through a current-sense resistor (R_CS) in series with Q_L source and a peak current threshold (V_CST) in the current loop controls the peak current variation. Due to the nature of transition-mode (TM) operation, lowering the peak current with lighter load conditions results in higher switching frequency. When the load current increases to an over-power condition (I_O(OPP)) where V_CST correspondingly reaches or exceeds an OPP threshold (V_CST(OPP)) of the peak current loop, the OPP fault response will be triggered after a 160-ms timeout (except not in UCC28781A, where the OPP timer function is always disabled). The RUN signal stays high in AAM, so the half-bridge driver remains active.

Figure 7-30 PWM Pattern in AAM