ZHCSLD2E may   2020  – july 2023 UCC28782

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 描述
  5. Revision History
  6. Device Comparison Table
  7. Pin Configuration and Functions
    1.     Pin Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Detailed Pin Description
      1. 8.3.1  BUR Pin (Programmable Burst Mode)
      2. 8.3.2  FB Pin (Feedback Pin)
      3. 8.3.3  REF Pin (Internal 5-V Bias)
      4. 8.3.4  VDD Pin (Device Bias Supply)
      5. 8.3.5  P13 and SWS Pins
      6. 8.3.6  S13 Pin
      7. 8.3.7  IPC Pin (Intelligent Power Control Pin)
      8. 8.3.8  RUN Pin (Driver and Bias Source for Isolator)
      9. 8.3.9  PWMH and AGND Pins
      10. 8.3.10 PWML and PGND Pins
      11. 8.3.11 SET Pin
      12. 8.3.12 RTZ Pin (Sets Delay for Transition Time to Zero)
      13. 8.3.13 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
      14. 8.3.14 BIN, BSW, and BGND Pins
      15. 8.3.15 XCD Pin
      16. 8.3.16 CS, VS, and FLT Pins
    4. 8.4 Device Functional Modes
      1. 8.4.1  Adaptive ZVS Control with Auto-Tuning
      2. 8.4.2  Dead-Time Optimization
      3. 8.4.3  EMI Dither and Dither Fading Function
      4. 8.4.4  Control Law across Entire Load Range
      5. 8.4.5  Adaptive Amplitude Modulation (AAM)
      6. 8.4.6  Adaptive Burst Mode (ABM)
      7. 8.4.7  Low Power Mode (LPM)
      8. 8.4.8  First Standby Power Mode (SBP1)
      9. 8.4.9  Second Standby Power Mode (SBP2)
      10. 8.4.10 Startup Sequence
      11. 8.4.11 Survival Mode of VDD (INT_STOP)
      12. 8.4.12 Capacitor Voltage Balancing Function
      13. 8.4.13 Device Functional Modes for Bias Regulator Control
        1. 8.4.13.1 Mitigation of Switching Interaction with ACF Converter
        2. 8.4.13.2 Protection Functions for the Bias Regulator
        3. 8.4.13.3 BIN-Pin Related Protections
        4. 8.4.13.4 BSW-Pin Related Protections
      14. 8.4.14 System Fault Protections
        1. 8.4.14.1  Brown-In and Brown-Out
        2. 8.4.14.2  Output Over-Voltage Protection (OVP)
        3. 8.4.14.3  Input Over Voltage Protection (IOVP)
        4. 8.4.14.4  Over-Temperature Protection (OTP) on FLT Pin
        5. 8.4.14.5  Over-Temperature Protection (OTP) on CS Pin
        6. 8.4.14.6  Programmable Over-Power Protection (OPP)
        7. 8.4.14.7  Peak Power Limit (PPL)
        8. 8.4.14.8  Output Short-Circuit Protection (SCP)
        9. 8.4.14.9  Over-Current Protection (OCP)
        10. 8.4.14.10 External Shutdown
        11. 8.4.14.11 Internal Thermal Shutdown
      15. 8.4.15 Pin Open/Short Protections
        1. 8.4.15.1 Protections on CS pin Fault
        2. 8.4.15.2 Protections on P13 pin Fault
        3. 8.4.15.3 Protections on RDM and RTZ pin Faults
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application Circuit
      1. 9.2.1 Design Requirements for a 65-W USB-PD Adapter Application
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Bulk Capacitance and Minimum Bulk Voltage
        2. 9.2.2.2 Transformer Calculations
          1. 9.2.2.2.1 Primary-to-Secondary Turns Ratio (NPS)
          2. 9.2.2.2.2 Primary Magnetizing Inductance (LM)
          3. 9.2.2.2.3 Primary Winding Turns (NP)
          4. 9.2.2.2.4 Secondary Winding Turns (NS)
          5. 9.2.2.2.5 Auxiliary Winding Turns (NA)
          6. 9.2.2.2.6 Winding and Magnetic Core Materials
        3. 9.2.2.3 Clamp Capacitor Calculation
          1. 9.2.2.3.1 Primary-Resonance ACF
          2. 9.2.2.3.2 Secondary-Resonance ACF
        4. 9.2.2.4 Bleed-Resistor Calculation
        5. 9.2.2.5 Output Filter Calculation
        6. 9.2.2.6 Calculation of ZVS Sensing Network
        7. 9.2.2.7 Calculation of BUR Pin Resistances
        8. 9.2.2.8 Calculation of Compensation Network
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1  General Considerations
      2. 11.1.2  RDM and RTZ Pins
      3. 11.1.3  SWS Pin
      4. 11.1.4  VS Pin
      5. 11.1.5  BUR Pin
      6. 11.1.6  FB Pin
      7. 11.1.7  CS Pin
      8. 11.1.8  BIN Pin
      9. 11.1.9  BSW Pin
      10. 11.1.10 AGND Pin
      11. 11.1.11 BGND Pin
      12. 11.1.12 PGND Pin
      13. 11.1.13 EP Thermal Pad
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  14. 13Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

Output Filter Calculation

The bulk output capacitor of active clamp flyback (ACF) converters, CO1 of the primary-resonance ACF or CO2 of the secondary-resonance ACF, is often determined by the load-step transient-response requirement from no-load to full-load transition. For a target output voltage undershoot (ΔVO) with the load step-up transient of ΔIO, the minimum bulk output capacitance (CO(MIN)) can be expressed as

Equation 42. GUID-1C5BA6DC-F286-44BC-AD5D-AF22D98544A6-low.png

where tRESP is the response time delay from the moment ΔIO is applied to the moment when IFB falls below 10 μA. At ~10 μA, full power is available to prevent further drop of VO and to recharge CO. The response delay time consists of the time for the secondary regulator to stop driving the opto-coupler input plus the time for the opto-coupler output transistor to turn off. RCo is the equivalent series resistance (ESR) of the output capacitor CO.

The output filter inductor (LO) is an essential component for the secondary-resonance ACF, not only to filter the large switching voltage ripple across CO1 but also to decouple the effect of CO2 on the resonant period. The sum of LO impedance, ESR of CO2 (RCo2), and CO2 impedance at minimum switching frequency (fSW(MIN)) must be much higher than CO1 impedance at the same frequency to force most of switching resonant current to flow through CO1 only. LO is chosen with minimal ESR to achieve minimal conduction loss.

Equation 43. GUID-F384B71D-E292-4632-B314-6CB421E4F765-low.gif

One benefit of lowering the ESR on CO1 (RCo1) is to help to reduce the switching ripple on the output voltage. Another benefit is reducing the conduction loss of CO1 for the secondary-resonance ACF converter. However, the issue is that the damping between LO and CO1 is weakened. Without proper damping, the magnitude of low-frequency resonant ripple between LO and CO1 enlarges output ripple, affects the loop stability, and affects the operation of synchronous rectifier (QSEC). The secondary-resonance ACF converter is the most vulnerable since CO1 with low capacitance significantly weakens the damping. To resolve this issue, it is found that a serial damping network formed by LDAMP and RDAMP is a very effective way to minimize the impact. However, too much damping results in noticeable conduction loss increase and full-load efficiency drop. Therefore, it is recommended that LDAMP and RDAMP should be higher than the theoretical strong damping value as the following equations suggest. Even though the damping network is an additional component, the physical size or the footprint is much smaller than LO, not only because of the small value but also the wide availability of small-size chip inductors with high winding resistance can provide "free" RDAMP. For the 65-W secondary-resonance ACF design with primary GaN FETs and a polymer-type CO2, when a 0.68-µH chip inductor is in parallel with a 1-µH output filter inductor, there is only 0.15% full-load efficiency drop at 90-V AC input, and there is a negligible efficiency difference at 230-V AC input.

Equation 44. GUID-C7570382-E8DD-44CE-89EA-7AA6D4B700AB-low.gif
Equation 45. GUID-459A37BF-BE32-46C0-9956-601CCF69C734-low.gif

The equation for RDAMP assumes that CO2 >> CO1. Select a standard component available with parameter values that satisfy both of these two equations. It is usually not necessary to use two separate components.