ZHCSLD2E may 2020 – july 2023 UCC28782
PRODUCTION DATA
UCC28782 contains six modes of operation summarized in Table 8-1. Starting from heavier load, the AAM mode forces PWML and PWMH into complementary switching with ZVS tuning enabled. ABM mode generates a group of PWML and PWMH pulses as a burst packet, and adjusts the burst off-time to regulate the output voltage. At the same time, the burst frequency variation is confined above 20kHz by adjusting the number of PWML and PWMH pulses per packet to mitigate audible noise and reduce burst output ripple. In LPM, SBP1, and SBP2 modes, PWMH and the ZVS tuning loop are disabled, so the converter operates in valley-switching. The survival mode is to maintain VVDD higher than VVDD(OFF) in a long burst off time, and also performs the clamping capacitor balancing function to reduce the voltage stress of the secondary-side rectifier.
MODE | OPERATION | PWMH | ZVS | |
---|---|---|---|---|
AAM | Adaptive Amplitude Modulation | ACF operation with PWML and PWMH in complementary switching | Enabled | Yes |
ABM | Adaptive Burst Mode | Variable fBUR > fBUR(LR), ACF operation in complementary switching | Enabled | Yes |
LPM | Low Power Mode | Fix fBUR ≈ fLPM, valley-switching | Disabled | No |
SBP1 | First StandBy Power Mode | Variable fBUR between fSBP2(LR) and fSBP2(UP), valley-switching | Disabled | No |
SBP2 | Second StandBy Power Mode | Variable fBUR < fSBP2(UP) as VBUR < 0.9 V; Variable fBUR < fSBP2(LR) as VBUR > 0.9 V; Both are in valley-switching | Disabled | No |
INT_STOP | Survival Mode | When VVDD < VVDD(OFF) + VVDD(PCT), a series of PWML pulses followed by a long PWMH pulse is generated | Enabled in the last switching cycle of a survival-mode burst packet | No |
Figure 8-24 and Figure 8-25 show the critical parameter changes among the five operating modes, where VCST is the peak current threshold compared with the current-sense voltage from the CS pin, fSW is the switching frequency of PWML, fBUR is the burst frequency, and NSW is the pulse number of PWML cycles per burst packet. Figure 8-24 represents the control mode difference under the two VS-pin voltage ranges, when the IPC-pin voltage is less than 0.9 V or IPC is connected to AGND. Figure 8-25 illustrates the modified control mode, when the IPC-pin voltage setting is higher than 0.9 V. The following section explains the detailed operation of each mode. The VS-pin voltage and IPC-pin voltage effects will also be introduced in the following section.